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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Running a Salesforce

I decided to run some posts on different areas of companies, and what I have found…

• 10 min read
sales , salesforce , business development , sales management

System, PCB, & Package Design 

Designing Data Bus with DDR5 Technology Today? Yes, It Is Possible!

Many system designers have been working with DDR4 RAM components in the past couple…

• 4 min read
ddr5 , AMI , Memory interface , IBIS , IBIS-AMI , DDR , Sigrity

System, PCB, & Package Design 

Improve High-Speed Serial Link Design with IBIS-AMI Backchannel Simulation

As signal integrity engineers, we know adaptive equalization is used in today’s multi…

• 3 min read
Serial link analysis , Backchannel Simulation , IBIS-AMI , SerDes , Sigrity , SystemSI

Verification

Cadence Collaborates with Test & Verification Solutions on Portable Stimulus

The Cadence® Connections® Verification Program brings together a worldwide network…

• 2 min read
CDNLive , Test , DVcon , pss , verification

System, PCB, & Package Design 

Dude, Where Are Your Files?

Let me tell you a funny story. We’ve been working with an outside research agency…

• 2 min read
Engineering Data Management , data management , Work in Process Data , Work in Progress Data , ECAD data , EDM , PCB design

Breakfast Bytes

Why You Shouldn't Trust Ken Thompson

I wrote yesterday about the two exploits, Spectre and Meltdown . I think that the…

• 7 min read
security , unix , thompson

The India Circuit

A Hackathon to Remember

A few weeks ago I wrote a blog about face recognition . Coincidentally, face recognition…

• 2 min read
Vishwakarma Institute of Technology , VLSI & Embedded Systems Design Conference , Tensilica , Tensilica Xtensa

Breakfast Bytes

Spectre and Meltdown: An Update

I wrote an extra Breakfast Bytes post a couple of weeks ago about Spectre and Meltdown…

• 10 min read
security , Intel , meltdown , AMD , x86 , Spectre , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Challenges for SoCs Integrating PCI Express…

In this week's Whiteboard Wednesdays video, Nick Heaton, Distinguished Engineer,…

• less than a min read
Whiteboard Wednesdays , SoC , PCI Express , verification

Analog/Custom Design

Virtuosity and Virtuoso Video Diary: Onwards and Upwards

Looking back at 2017, I note with satisfaction that it was a phenomenal year of blogging…

• 3 min read
Cadence blogs , custom/analog , Virtuoso , RF design , Virtuosity , Virtuoso Video Diary , Custom IC Design , Custom IC

Breakfast Bytes

IEDM Short Course: After 5nm

The Sunday of IEDM is always two full-day short courses. One is on the future of…

• 7 min read
feol , 5nm , beol , IEDM , DTCO

Verification

This Was 2017, Looking Forward 2018

With 2017 just out of the door, this is a good time to stop for a few minutes, look…

• less than a min read
Specman , Functional Verification

Breakfast Bytes

Mobile World Congress in One Keynote

It was CES last week. Generally, this is not an event about mobile, mainly because…

• 8 min read
5G , baidu , CES2018 , Verizon , Qualcomm , mobile

Breakfast Bytes

CES Keynotes: Cars, Flying Cars, Dancers, Music, Lights...and Sustainability

As I said yesterday , it was the Consumer Electronics Show this week. I attended…

• 10 min read
quantum computing , Automotive , Intel , CES , Ford

Verification

CRAFTing Your Aero/Defense UVM Testbench the Easy Way

So you want to build an automated testbench for your aero/defense project, eh? Luckily…

• 2 min read
Functional Verification , VWB , online tool , automated testbench , craft

Breakfast Bytes

CES Review: Rain...and Some Consumer Electronics

I have been at the Consumer Electronics Show (CES) all week. For 116 days through…

• 7 min read
Automotive , Consumer Electronics , CES , CES2018 , virtual reality , augmented reality

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (5 of 8)

Efficient Interconnect Extraction Once physical layout is complete, (or at least…

• 3 min read
Serial link analysis , SI , Multi-Gigabit , Interconnect Extraction , IBIS-AMI , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

What's For Breakfast? Video Preview January 15th to 19th 2018

https://youtu.be/MPkAPCQyFvY Coming from Consumer Electronics Show, Las Vegas…

• less than a min read
5G , meltdown , ken thompson , JUG , CES2018 , Spectre , 5nm , what's for breakfast? , JasperGold

Verification

User Extensions to DUT Error

A question was raised to stackoverflow about how can one extend the dut _error()…

• 2 min read
Specman , e code , advanced verification , e language
CDNS - Fix Layout Hompage