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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Computational Fluid Dynamics

Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpr…

Authors: Akio Takamura, Chief Engineer, Honda R&D, and Benoit Mallol, Head of Marine…

• 3 min read
CFD , Automotive , Computational Fluid Dynamics , fluid dynamics , Meshing , simulation

定制IC芯片设计

Virtuoso 视频日记: 下一件大事 - ADE Verifier与Cadence vManager合作

今天的博客重点介绍了ADE Verifier的最新增强功能。这个博客我们每周二和周四发布的迷你博客系列的一部分，以涵盖 Virtuoso®ADE Assembler…

• 1 min read
verifier , Chinese blog , ICADVM18.1 , Functional Verification , Formalized Verification , vPlan , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso Video Diary , ADE Blog Series , mixed signal , mixed-signal design , Custom IC Design , Custom IC , ADE Verifier , IC6.1.8 , vManager , verification

Verification

Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Thin…

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but…

• 2 min read
DAC 2019 , Semiconductor , cadence cloud

Analog/Custom Design

Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

Really, can Virtuoso bind strict? And what does that mean? Read along to find out…

• 2 min read
Update Binding , ICADVM18.1 , Layout XL Environment Variables , cdsenv , Virtuoso , Check Against Source , bindStrict , Custom IC Design , Update Components And Nets , Binder , IC6.1.8 , Virtuoso Layout Suite XL , binding

Breakfast Bytes

Computer Scientist Alan Turing to Be on British £50 Note

Last week the Bank of England announced that the new £50 note will have Alan Turing…

• 7 min read
bletchley park , turing award , alan turing

Whiteboard Wednesdays

Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols…

• less than a min read
Whiteboard Wednesdays , PHY IP , ONFI 4.x

Breakfast Bytes

Virtuoso Meets Maxwell

When I was a postgraduate at Edinburgh University, my office was in the James Clerk…

• 3 min read
RF , maxwell , Virtuoso

System, PCB, & Package Design 

IC Packagers: Correcting Die Orientations and Die Attachments

When you add a die component to your SiP Layout design, you must identify both its…

• 3 min read
APD , SiP Layout

定制IC芯片设计

Virtuosity: 我的 Checks 通过还是没有运行？

今天的博客重点介绍 Checks/Asserts 结果显示和 Summary 表。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分，以涵盖…

• 1 min read
Chinese blog , ADE Explorer , Virtuosity , Custom IC Design , ADE Assembler

Analog/Custom Design

Tales from DAC: MediaTek's Experience with Spectre X Simulator

MediaTek recently gave the new Spectre X Simulator a try, and they talked about their…

• 1 min read
Cadence Theater , DAC 2019 , mediatek , spectre x

System, PCB, & Package Design 

DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

Ah, the office temperature – that eternal debate. As in many offices, ours has some…

• 2 min read
allegro edm , PCB design

Analog/Custom Design

Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where?

Here I come back with another episode of TILP of the Virtuoso Meets Maxwell series…

• 4 min read
ICADVM18.1 , die export , Virtuoso Meets Maxwell , Virtuoso RF , die , Layout , Multitech , TILP , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

Passwords and Multi-Factor Authentication

I recently came across an interesting piece written by Microsoft's Alex Weinert,…

• 6 min read
security , passwords , two factor authentication

Breakfast Bytes

Sunday Brunch Video for 21st July 2019

https://youtu.be/JHWXXezFMU8 Made at Krakow, Poland (camera Gary Bengier) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

The First Computer on the Moon

I am sure you can't fail to have noticed that tomorrow is the 50th anniversary of…

• 7 min read
moon landing , NASA

PCB、IC封装：设计与仿真分析

关于PCB安装孔所需了解的一切

安装孔似乎很简单——只需将印刷电路板安装到外壳或表面上，选择一个适合电路板以及待安装表面的螺丝尺寸，然后根据此规格钻孔即可。 但与印刷电路板中其他设计一样，当增加高速信号并减小形状因子后…

• less than a min read
PCB , Chinese blog , 钻孔 , PCB设计 , 中文 , 过孔 , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuosity: Introducing Automated Device Placement and Routing in Virtuoso

This blog provides an overview of the fully automated device-level placement and…

• 3 min read
ICADVM18.1 , Automated Device-Level Placement and Routing , VPR , Automatic Placement , Advanced Node , Layout EXL , APR , Auto P&R , Virtuoso , Virtuosity , Virtuoso Placement , Custom IC Design

Verification

Tales from DAC: Cadence, AI, and You

Complexity is driving the urgency for advanced artificial intelligence systems more…

• 2 min read
Functional Verification , Cadence Theater , DAC 2019 , Tensilica , AI

定制IC芯片设计

Virtuosity: 模拟设计环境中的最重要的3个后仿改进功能

今天的博客重点介绍了后仿流程的最新增强功能。 这些增强功能解决了许多长期存在的问题，例如原理图和版图命名的匹配，绘制端口电压和DSPF文件扫描。 这个博客是我们每周发布两次…

• 1 min read
Chinese blog , ADE Explorer , post-layout , DSPF , Virtuoso Analog Design Environment , postlayout , Virtuosity , ADE Assembler
CDNS - Fix Layout Hompage