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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuosity: A Guide to Bindkeys for Interactive and Assisted Routing Commands

I'm sure you are well-versed with the benefits of using bindkeys. So, to have a better…

• 2 min read
Interactive Routing , Create Wire , custom/analog , Virtuoso Space-based Router , VSR , Routing , Create Stranded Wire , Interactive and Assisted Routing , Wire Editing , Mixed-Signal , Layout , Virtuoso , Virtuosity , mixed signal , createbus , Custom IC Design , Assisted Routing , Virtuoso Layout Suite , Custom IC , Interactive Wire Editing

Breakfast Bytes

Liberate Trio: Characterization Suite in the Cloud

Years ago, library characterization used to be fairly straightforward. The library…

• 3 min read
characterization , liberate trio , cloud , cadence cloud , ARM

Breakfast Bytes

Overcoming Bias in Computer Vision

At the recent Embedded Vision Summit, Will Byrne gave a presentation Overcoming Bias…

• 6 min read
stereotype , embedded vision , bias

The India Circuit

Thirty Years As One Team

Last week, Cadence was recognized as No 28 in the “Best Companies to Work For” study…

• 3 min read
Great Place To Work Institute , GPTW , Cadence India , Best Companies to Work For

Breakfast Bytes

Want to Go on a Second Date?

Yesterday I told you about the Doomsday algorithm in my post Doomsday in 1900 Was…

• 6 min read
offtopic , DATE , microsoft

Breakfast Bytes

Doomsday in 1900 Was a Wednesday

Cadence is off today, so time for an off-topic post. In my post Short Papers last…

• 6 min read
offtopic , DATE , john conway

SoC and IP

Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband…

• 1 min read
DSP , IoT , Fusion , ip cores , Tensilica , nb-iot

Breakfast Bytes

What's For Breakfast? Video Preview July 9th to 13th 2018

https://youtu.be/d04TXTJKx5o Coming from Cadence EBC (camera Lan Ly) Monday: ESD…

• less than a min read
semicon , imec , 55DAC , esd alliance , palladium cloud

Breakfast Bytes

/* You Are Not Expected to Understand This */

The title of this post, you are not expected to understand this, is one of the most…

• 7 min read
ken thompson , unix , bug , john lyons , dennis ritchie

Breakfast Bytes

A History of PSS

In a remark attributed to Otto von Bismarck (or perhaps misattributed), it is said…

• 6 min read
Perspec , pss , portable stimulus standard , verification

Verification

Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

Welcome back to our series on cloud verification solutions. This is the final part…

• 2 min read
security , Functional Verification , cadence cloud , xcelium , palladium cloud

Verification

UVM-ML- Managers’ Freedom of Choice

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is…

• 5 min read
Specman , Specman/e , UVM-ML , Specman e , UVM multi-language , UVM-e , UVM ML , multi-language , multi-language UVM , multi-language verification , verification

Breakfast Bytes

DAC Wednesday: Denali, Patterson on Architecture, Rowen on Deep Learning, Analog…

Tuesday evening finished with the Denali Party. Since it's 8 years since Cadence…

• 13 min read
Analog artist , analog , isa , reliability

Breakfast Bytes

What's For Breakfast? Video Preview July 2nd to 6th 2018

https://youtu.be/QoFQImb0xk4 Coming from DAC (camera Sean) Monday: /* You are…

• less than a min read
liberate trio , doomsday , john conway , embedded vision , cloud , cadence cloud

SoC and IP

Chip Dis-integration

I was asked the following question recently. No longer are we seeing increasing…

• 5 min read
chiplets , IoT , Design IP and Verification IP , moore's law , 2.5D interposer

Breakfast Bytes

DAC Tuesday: IBM's AI, Jay's Wall Street View, Lip-Bu's Chat, Monster Chips

The second day of DAC needed several clones of me at lunchtime. Lip-Bu Tan's turn…

• 14 min read

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to Functional Safety From an IP Supplier

In this weeks Whiteboard Wednesdays Divya Kalimuthu speaks about ISO 26262 from the…

• less than a min read
Whiteboard Wednesdays , functional safety

The India Circuit

The New India: Rise Of The Cashless Wallets

Can India really ever go cashless? This was one of the topics that was discussed…

• 3 min read
Government of India , cashless economy , digital india , Ezetap , demonetization , make in india

Breakfast Bytes

DAC Monday: Amazon's Things, Handel's Megadesign, Cooley's Troublemakers

Another year, and another DAC. As usual, the proceedings kicked off on Sunday night…

• 14 min read
dac55 , DAC , handel jones , Cooley , ibs , verification
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