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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Breakfast Bytes

DesignCon and Target Impedance

I was DesignCon recently. It is a bit of a weird conference, since it covers a wide…

• 3 min read

Breakfast Bytes

Mobile World Congress: Hololens and More

From February 27th to March 2nd it is Mobile World Congress (MWC) in Barcelona, Spain…

• 2 min read
barcelona , Mobile World Congress , Tensilica , #mwc17

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2017

https://youtu.be/RIkl4O5Q-V4 Coming from inside the Intel Museum, Santa Clara…

• less than a min read
Intel , spie advanced lithography , law enforcement , DVcon , mobile , privacy , intel investor day , stingray

SoC and IP

Three New Memory Trends in Enterprise Data Centers

You might have seen the graph below about the increase in monthly internet traffic…

• 5 min read
Design IP , Memory , DDR4 , flash , memory IP , DDR , memories

Digital Design

Making Hardware Design Great Again in 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Breakfast Bytes

Putting a Rocket Under Incisive

When Cadence first acquired RocketSim, I wrote a post, Omnia Simulation in Tres Partes…

• 3 min read
SystemVerilog , Incisive , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Memory Models Runtime Control

In this week's Whiteboard Wednesdays video, Dharini SubashChandran explains how to…

• less than a min read
runtime , Whiteboard Wednesdays , IP , memory IP , Dharini SubashChandran

Breakfast Bytes

Cat-NB1 and HaLow Wireless Links Powered by Tensilica Fusion F1

A generic Internet of Things (IoT) device consists of some sensors, some computations…

• 4 min read
tensilica fusion f1 , tensilica fusion , tensilica f1 , Tensilica , narrowband , nb-iot , commsolid

Verification

What Sort of Bugs Does Portable Stimulus Find?

In a recent blog post , we discussed some general concepts of bugs, problems, issues…

• 3 min read
hardware-software co-verification , uvm , Low Power , pswg , debug , Functional Verification , System Design and Verification , embedded software , Emulation , Accellera , Hardware/software co-verification , debugging , portable stimulus , interrupts

Breakfast Bytes

Neural Networks and the Future

The Panel Session The recent embedded neural network symposium held at Cadence…

• 8 min read
deep learning , enns , neural networks , autonomous vehicles , debugging

Breakfast Bytes

Chris Rowen: Neural Networks—The New Moore's Law

In addition to being the master of ceremonies for the recent embedded neural network…

• 3 min read

Breakfast Bytes

Kunle Olukotun: Scaling Machine Learning Performance

The keynote at the recent Embedded Neural Network Symposium held recently at Cadence…

• 5 min read
buckwild! , Delite , plasticine , hogwild! , neural networks

Whiteboard Wednesdays

Whiteboard Wednesdays - Coherent Interconnect Verification Challenges

In this week's Whiteboard Wednesdays video, Nimrod Reiss discusses the challenges…

• less than a min read
Verification IP , Whiteboard Wednesdays , throughput , VIP , latency , snoop filtering , Nimrod Reiss , interconnect verification

Breakfast Bytes

Jeff Bier: When Every Device Can See

Jeff Bier is the founder of the Embedded Vision Alliance, which runs the annual Embedded…

• 3 min read
deep neural network , deep learning , Embedded Vision Alliance , machine learning , neural network , machine vision

Academic Network

EDA Workshop in Taiwan

Cadence Academic Network recently participated in the 2016 IEEE and CEDA Workshop…

• 1 min read
academic workshop , academia

Breakfast Bytes

What's For Breakfast? Video Preview February 20th to 24th 2017

https://youtu.be/EVZ4T8TPim8 Coming from inside a Microsoft Hololens Monday…

• less than a min read
holoens , DesignCon , spie advanced lithography , Mobile World Congress , MWC , rocketsim , target impedance , parallel simulation

Analog/Custom Design

Virtuoso Video Diary: Eye Masks

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and…

• 4 min read
Eye Mask , Analog Design Environment , Eye , ADE GXL , ViVa-XL , ADE Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuoso Video Diary

Breakfast Bytes

The Second Embedded Neural Network Symposium

A couple of weeks ago, Cadence held the second embedded neural network symposium…

• 8 min read
deep neural networks , enns , dnn , embedded neural networks , neural networks

Breakfast Bytes

Integrated Bus Routing Solution

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there…

• 3 min read
integrated bus routing solution , grid-based routing , analog , Innovus , high frequency router
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