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The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

USB Developer Days – Turning Specifications into Applications

Each time I start working on an introductory paragraph for a new USB blog entry,…

• 2 min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Cadence and imec Announce World's First 5nm Tapeout

7nm is already passé it seems! Today Cadence and imec announced the tapeout of the…

• 4 min read
testchip , imec , Innovus , 5nm , 7nm , SAQP , EUV

Breakfast Bytes

The Beginning of Breakfast Bytes

Yes, it’s true. The Cadence gravitational field finally pulled me back and I am now…

• 1 min read
Paul McLellan , DAC , Jasper User Group , VSLI

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P5 DSP

In this week's Whiteboard Wednesday video, Dennis Crespo highlights the performance…

• less than a min read
security , Automotive , DSP , Vision P5 , Whiteboard Wednesdays , IP , Tensilica , mobile

SoC and IP

Ethernet Reaches into Ever More Application Spaces

I blog from time to time about what’s new in Ethernet. I have just returned from…

• 2 min read
HDD , 802.3bs , Automotive Ethernet , Ethernet , Design IP and Verification IP , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays—Meeting Automotive Memory and I/O Bandwidth Challenges

In this week's Whiteboard Wednesdays video, Charles Qi continues his discussion focused…

• less than a min read
Automotive , I/O , Whiteboard Wednesdays , IP , Memory , interfaces , bandwidth , high performance

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Pastemask DRC? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 Pastemask to Pastemask DRC now checks the ‘Package Geometry…

• less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

SoC and IP

Cadence Announces the First MIPI I3C Verification IP!

The MIPI Alliance has developed dozens of specifications, standardizing all interfaces…

• 1 min read
Verification IP , MIPI Alliance , MIPI , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - A Peek Inside Future Automotive Networks

In this week's Whiteboard Wednesdays video, Charles Qi explains future automotive…

• less than a min read
Whiteboard Wednesdays , automotive engineering , Automotive Ethernet , automotive electronics , automotive IP

Life at Cadence

Cadence Celebrates Women’s Day in India

Cadence India celebrated Women’s Day across all four sites on March 9th. Women’s…

• less than a min read
Insights on Culture , inclusion , Women's Day , HeforShe , Cadence India

Whiteboard Wednesdays

Whiteboard Wednesdays - Why a DSP is the Right Choice for Imaging and Vision Alg…

In this week's Whiteboard Wednesday's video, the third in a three-part series, Pulin…

• less than a min read
DSP , Whiteboard Wednesdays , IP , vision algorithms , Tensilica , imaging algorithms

Verification

Incisive vManager Free Video Training

The Incisive vManager tool for professional verification planning and management…

• 2 min read
Functional Verification , Cadence Online Support , Incisive , training , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Replace Padstack? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 ‘ Replace Padstack ’ command is now available as a context…

• less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , Routing , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

Generate Daisy Chain Patterns for Test Vehicles and Other Applications Using the…

With increasing design complexity comes the need to create test vehicles to qualify…

• 5 min read
Co-Design , 16.6 , manufacturing , early adopter , SiP Layout , substrate design tools , Physical layout and co-design , daisy chain

Whiteboard Wednesdays

Whiteboard Wednesdays—DSP for Automotive Applications

In this week's Whiteboard Wednesday's video, Charles Qi discusses how Cadence scaleable…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , Tensilica

Verification

Accelerating the Next Big Shift in Verification

Today Cadence announced that we are aligning our proposal to the Accellera Portable…

• 5 min read
pswg , scenario , UML , software-driven verification , Accellera

Whiteboard Wednesdays

Whiteboard Wednesdays - Addressing SoundWire Design Challenges

In this week's Whiteboard Wednesdays video, the second in a two-part series, Charles…

• less than a min read
Design IP , Whiteboard Wednesdays , software design challenges , MIPI SoundWire

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Line Width Retention? 16.6 Has It!

Currently, user line width overrides are permitted during the Add Connect command…

• 1 min read
PCB Layout and routing , 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability…

As package substrates continue to get more complex, often resembling silicon as much…

• 4 min read
IC Packaging and SiP Design , GDSII , DRC , stream , 16.6 , SPB , PVS
CDNS - Fix Layout Hompage