• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Cadence Blogs

Stay up to date with our latest corporate and technology blog posts

Explore the Cadence Forums to find and exchange in-depth technical information.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

    Popular Search: Corporate NewsArtificial IntelligencePCB DesignCFD
Featured

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
Corporate 22 Jun 2026 • 8 min read
featured , physical ai , HGR , AI , Honda
cdns - all_blogs_categories

  • All 6422
  • Corporate News 266
  • Life at Cadence 204
  • Academic Network 169
  • Analog/Custom Design 804
  • Artificial Intelligence 27
  • Cloud 23
  • Computational Fluid Dynamics 374
  • Data Center 60
  • Digital Design 462
  • Learning and Support 63
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1016
  • Verification 1326
  • Cadence Japan 18
  • Physical Systems Simulation 24

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Verification

OVM is "Open" for Business

Open things are just curiosities until the ecosystem figures out how to turn them…

Adam Sherer 29 Jul 2008 • 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , Testbench simulation , OVM , OVMWorld

RF Engineering

Tip of the Week: Why Do Shooting and Harmonic Balance Phase Noise Results Differ…

Question: You are simulating your VCO in SpectreRF. You ran your PSS + Pnoise (noisetype…

Tawna 29 Jul 2008 • 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Analog/Custom Design

Is mixed-signal simulation a fantasy?

The world is a mixed-signal one, or at least that's what were told. The concept of…

NewYorkSteve 28 Jul 2008 • less than a min read
mixed-signal simulators , Custom IC Design

Verification

Transaction-Based Acceleration - Second generation

Transaction-Based Acceleration is becoming more and more important as an extension…

Ran Avinun 28 Jul 2008 • less than a min read
System Design and Verification

RF Engineering

Tip of the Week: Please explain in more practical (less theoretical) terms the concept…

Question: From spectre -h pnoise. I find the definition for oscillator linewidth…

Tawna 25 Jul 2008 • 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

What's good about CheckSysConf? Plenty!

While I suspect that many of our customers have used or heard about the CheckSysConf…

Jerry GenPart 23 Jul 2008 • 3 min read
CheckSysConf , PCB design

Digital Design

Who Designed the iPhone?

When people ask you what you do for a living, is your response as clumsy as mine…

BobD 23 Jul 2008 • 1 min read
Digital Implementation , iPhone

System, PCB, & Package Design 

Second Generation PCI Express spreading roots

According to Jag Bolaria of the Linley Group, the 5 Gbps version of PCI Express…

Maxwell86 22 Jul 2008 • less than a min read
PCB Signal and power integrity , SPB , SerDes , PCB design

Digital Design

Statistical Timing Analysis - Has its time arrived?

At 45nm chip designs, manufacturing and process control becomes increasingly difficult…

RahulD 21 Jul 2008 • 2 min read
Static timing analysis , STA , Digital Implementation , SSTA , corner analysis

Verification

Trip to SoCal "techtorials" on CDV

Just finished packing for a quick trip to Southern California to help kickoff a round…

jvh3 20 Jul 2008 • 1 min read
Functional Verification , Coverage-Driven Verification , CDV

Verification

Is anybody out there a Software Verification Engineer?

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I…

jasona 16 Jul 2008 • 3 min read
co-verification engineer , System Design and Verification , EDA

System, PCB, & Package Design 

Did you know? Enriched schematic content available in PDF files from DEHDL (ConceptHDL…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various…

Jerry GenPart 16 Jul 2008 • 1 min read

RF Engineering

Measuring Transistor ft

So let’s consider a practical example of creating test benches and performing measurements…

Art3 16 Jul 2008 • 5 min read
Measuring Transistor ft , RF design

System, PCB, & Package Design 

Shocking Technologies Becomes a Cadence Connections Member

In an announcement concurrent with Semicon West 2008, Shocking Technologies has …

Maxwell86 14 Jul 2008 • less than a min read
PCB Layout and routing , electrostatic discharge (ESD) dangers , Shocking Technologies , SPB , PCB design

Verification

C-to-Silicon Compiler Launch

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level…

Ran Avinun 14 Jul 2008 • 1 min read
high-level synthesis adoption , C-to-Silicon Compiler

RF Engineering

Inductors On Demand, at least one RF design task can be really automated!

Inductors, transformers and transmission lines are critical components in any high…

Hany 13 Jul 2008 • 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso PCD , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design , Virtuoso Passive Component Designer , wireless integrated circuit verification

Digital Design

Customer Experiences With Low-Power Design

Hello and welcome to the new Cadence community site, and my first blog post. You…

archive 13 Jul 2008 • 4 min read
Low-Power , Logic Design , Digital Implementation , The Power Forward Initiative

Verification

Emulation Drivers - A growing set of selection criteria

Some say that the growth of the emulation market in last few years was driven by…

Ran Avinun 13 Jul 2008 • 2 min read
Acceleration , System Design and Verification , Emulation , Hardware/software co-verification

System, PCB, & Package Design 

What's Good About Differential Pair Support in ASA?

What's Good About Differential Pair Support in ASA? Quite a bit actually! In…

Jerry GenPart 13 Jul 2008 • 1 min read
ASA , Allegro System Architect (ASA) , PCB design , Differential Pair Support
<>
CDNS - Fix Layout Hompage

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information