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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's good about Capture-CIS Digi-Key Integration?

So, what's good about Capture-CIS Digi-Key Integration? Quite a bit actually! This…

• 1 min read
Capture CIS , PCB design , Component Information Portal (CIP) , Digi-Key Integration

Digital Design

See you at CDNLive! Silicon Valley

Are you planning to attend this year's CDNLive! Silicon Valley 2008? Please leave…

• less than a min read
cadence.com community , First Encounter , CDNLive!

Verification

Putting a face on the OVM

As I recently blogged , there appears to be growing buzz over the Open Verification…

• 1 min read
CDNLive , Open Verification Methodology , OVM

RF Engineering

Tip Of the Week: analogLib mtline now has a cross sectional viewer when Type of Input…

Many users have indicated that it is challenging to correctly enter complex transmission…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Verification

Design space exploration

In his latest blog post Space Exploration ... design is , Grant Martin said that…

• 1 min read
high-level synthesis adoption , System Design and Verification , C-to-Silicon Compiler

Verification

Report from the CDV techtorials in SoCal

To follow-up on my previous post on the techtorials, I'm posting some photos from…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , coverage driven verification (CDV) , eRM

Verification

Flexibility Often Yields Unexpected Results

Often, when engineers set out to build something, the result is different from the…

• 4 min read
Functional Verification , Founders at Work Stories of Startups' Early Days , ISX (Incisive Software Extensions)

Verification

OVM is "Open" for Business

Open things are just curiosities until the ecosystem figures out how to turn them…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , Testbench simulation , OVM , OVMWorld

RF Engineering

Tip of the Week: Why Do Shooting and Harmonic Balance Phase Noise Results Differ…

Question: You are simulating your VCO in SpectreRF. You ran your PSS + Pnoise (noisetype…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Analog/Custom Design

Is mixed-signal simulation a fantasy?

The world is a mixed-signal one, or at least that's what were told. The concept of…

• less than a min read
mixed-signal simulators , Custom IC Design

Verification

Transaction-Based Acceleration - Second generation

Transaction-Based Acceleration is becoming more and more important as an extension…

• less than a min read
System Design and Verification

RF Engineering

Tip of the Week: Please explain in more practical (less theoretical) terms the concept…

Question: From spectre -h pnoise. I find the definition for oscillator linewidth…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

What's good about CheckSysConf? Plenty!

While I suspect that many of our customers have used or heard about the CheckSysConf…

• 3 min read
CheckSysConf , PCB design

Digital Design

Who Designed the iPhone?

When people ask you what you do for a living, is your response as clumsy as mine…

• 1 min read
Digital Implementation , iPhone

System, PCB, & Package Design 

Second Generation PCI Express spreading roots

According to Jag Bolaria of the Linley Group, the 5 Gbps version of PCI Express…

• less than a min read
PCB Signal and power integrity , SPB , SerDes , PCB design

Digital Design

Statistical Timing Analysis - Has its time arrived?

At 45nm chip designs, manufacturing and process control becomes increasingly difficult…

• 2 min read
Static timing analysis , STA , Digital Implementation , SSTA , corner analysis

Verification

Trip to SoCal "techtorials" on CDV

Just finished packing for a quick trip to Southern California to help kickoff a round…

• 1 min read
Functional Verification , Coverage-Driven Verification , CDV

Verification

Is anybody out there a Software Verification Engineer?

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I…

• 3 min read
co-verification engineer , System Design and Verification , EDA

System, PCB, & Package Design 

Did you know? Enriched schematic content available in PDF files from DEHDL (ConceptHDL…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various…

• 1 min read
CDNS - Fix Layout Hompage