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Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

IC Packagers: Variable Text Labels and Template Reuse

For many, the information labels always go in a consistent location in the design…

• 4 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

Colossus: the First Programmable Digital Electronic Computer

Today is the first day of the RSA security conference in San Francisco. I will be…

• 7 min read
colossus , national museum of computing , bletchley park , museum

Breakfast Bytes

DesignCon: The Future of Fiber Optic Communications

At the recent DesignCon, Chris Cole gave the keynote The Future of Fiber Optic Communications…

• 8 min read
Ethernet , silicon photonics , photonics , datacenter , networking

定制IC芯片设计

Virtuosity: Property Editor可用性增强功能

“可用性概念“在我们的生活中随处可见，基于这个概念而产生的产品，便于使用及访问，并且更吸引眼球。因此，为了不断提升产品的可用性，在Virtuoso® Layout…

• less than a min read
Chinese blog , ICADVM18.1 , Virtuoso Layout Suite L , Property Editor , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

Sunday Brunch Video for 23rd February 2020

https://youtu.be/CPNy6CjnvEs Made on my balcony (camera Carey Guo) Monday: President…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

年度网课：极致PCB设计全流程网课计划

“工欲善其事，必先利其器”，我们要高质高效完成PCB设计，除了有效的规划及设计策略外，还必须深入理解工具的使用方法和设计技巧。只有夯实这些基础，我们才能真正避免…

• less than a min read
Chinese blog , training , webinar , PCB设计 , 中文 , 直播网课 , online training

Digital Design

Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton…

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and…

• 3 min read
Liberate Trio Characterization , Unified Flow , Variation Modeling , artificial intelligence , ARM-based Graviton Processors , liberate blog , Amazon Web Services , Multi-PVT , Liberate LV , Liberate Variety , machine learning , aws , PVT corners , Liberate , Liberate Characterization Portfolio , TSMC OPI Ecosystem Forum 2019

Breakfast Bytes

DesignCon: Design for Security

At DesignCon, one of the keynotes was by Warren Savage titled Design for Security…

• 6 min read

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 1

This blog will take you on a short tour to the Cadence Education Services site, which…

• 4 min read
training bytes , Virtuoso , Virtuoso Video Diary , Virtuoso Layout

Breakfast Bytes

Getting on to the Internet in 1993

I recently listened to an a16z podcast about crypto. It was an interview by Katie…

• 7 min read
Internet , a16z , history

Breakfast Bytes

What If It's Not 5G, But Satellites?

What if the answer to next-generation communication is not 5G but space? Elon Musk…

• 5 min read
5G , Automotive , mobile , space

System, PCB, & Package Design 

IC Packagers: An Introduction to Via Arrays

Vias are present in every design (except maybe some lead frames and the very rare…

• 5 min read
Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: Training Insights - Improving SI/PI Simulation of DDR Interfaces at…

In the days of yore when life was simple, there was a world full of DRAMs (Dynamic…

• 2 min read
Allegro Package Designer , Sigrity , Allegro PCB Editor

The India Circuit

Playing for Good

Last Saturday, Cadence and Concern India Foundation hosted a very special event …

• 1 min read
5Cs , NXP Semiconductor , amadeus , Qualcomm

Breakfast Bytes

DVCon 2020 Preview

Coming up to the big conferences like DAC, I like to do one or more preview posts…

• 7 min read
DVcon , Accellera , pss

Breakfast Bytes

Sunday Brunch Video for 16th February 2020

https://youtu.be/uc_vrZsq-2I Made in Cadence parking lot (camera Steve Brown) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: PCB Electronics—Why Use Via Arrays?

We all know the ubiquitous via. What is it after all but a way to make electrical…

• 3 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

Quines on Valentine's

Monday is President's Day and Cadence is off so, as has become traditional, I write…

• 5 min read
offtopic

Analog/Custom Design

Virtuosity: Updated Virtuoso ADE Explorer and ADE Assembler RAKs in IC6.1.8/ICADVM18…

To show the latest features in IC6.1.8/ICADVM18.1 ISR9, we've updated the Rapid Adoption…

• 3 min read
ICADVM18.1 , ADE Explorer , Rapid Adoption Kit , RAK , stimuli , Virtuoso Analog Design Environment , Virtuosity , Custom IC Design , ADE Assembler , Stimuli Assignment form
CDNS - Fix Layout Hompage