Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Academic Network

Xtensa Design Contest 2015 in India

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University…

• less than a min read
Cadence Academic Network , Cadence India , Xtensa Design Contest , university program

Academic Network

Cadence Innovus Implementation System is Available to Academia

To support academia using the latest industry-standard tools, Innovus™ Implementation…

• 1 min read
Routing , academia , Innovus , implementation , Placement

Breakfast Bytes

Front-end Design Summit

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses…

• 4 min read
Genus , Encounter Test , manufacturing test , Joules , front end design summit , Test , front end design , Synthesis , power , Breakfast Bytes

Academic Network

Cadence Academic Network - The Next Generation

“University students around the world are using Cadence technology to learn and develop…

• 2 min read
Cadence interns , Cadence Academic Network , EDA , engineering

System, PCB, & Package Design 

What's Good About PCB Allegro Rules Developer and Checker? 16.6 Has It!

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker .…

• less than a min read
Constraint-driven PCB Design flow , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , High Speed , PCB Editor , High-Density Interconnect , Layout , PCB design , Allegro PCB Editor , differential pairs

Breakfast Bytes

Why Do Layout Designers Say "Stream Out"?

For the same reason we "hang up" our phones. When a layout designer saves a design…

• 6 min read
GDSII , Stream Out , Layout , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—DUT Verification with Cadence VIP

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly…

• less than a min read
DUT verification , Verification IP , Whiteboard Wednesdays , VIP

SoC and IP

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

• 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

Breakfast Bytes

Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and…

• 5 min read
EAD , FinFets , iPVS , Custom Routing , multi-patterning , Virtuoso , 10nm , modgens , color-aware layout , Breakfast Bytes

System, PCB, & Package Design 

Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro…

With metal density and balancing requirements getting stricter with every year that…

• 6 min read
Cadence Design Systems , SiP Design , 16.6 , IC package design , APD , Allegro Package Designer , manufacturing , SiP Layout , shapes

Breakfast Bytes

TSMC 3D. Red and Green Glasses Not Required

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations…

• 4 min read
CoWoS , 3DIC , info-pop , TSMC , InFO , info_s , Breakfast Bytes

Breakfast Bytes

Can You Pass As a Brit? Just Answer 3 Simple Questions

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 9 min read
thanksgiving , lbw , guy fawkes , gunpowder plot , glorious revolution , marmite

Breakfast Bytes

Voltus-Fi: Faithful Custom and Analog EMIR and Power Analysis

First things first. Voltus and Voltus-Fi are two separate products. They are both…

• 3 min read
Voltus-Fi , AMS , electromigration , custom , analog , Voltus , Virtuoso , analog mixed signal , IR drop , power , Breakfast Bytes , EMIR

SoC and IP

50 Gbps Ethernet is on the Way

Here is my report from the most recent IEEE 802.3 standards meeting, which was held…

• 2 min read
Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , Marris , 50G Ethernet

Verification

Cheating Tetris

Remember Tetris? We’ve all played it at some point in our lives. You know, the game…

• 2 min read
Verification Computing Platform , Palladium , Tetris , Emulation

Breakfast Bytes

The Design that Made ARM

I sat down with Simon Segars, the CEO of ARM last Friday. As I said yesterday, it…

• 4 min read
Simon Segars , ARM7TDMI , ARM , Breakfast Bytes

Breakfast Bytes

Happy 25th Birthday, ARM

This week is ARM's 25th anniversary. It is actually on Friday, the 27th, but since…

• 7 min read
ARM processor , Simon Segars , VSLI , ARM

Verification

A Coverage Time-Saving Tip

How often has this happened to you? You are re-using a part of a previous design…

• 2 min read
IMC , coverage , Incisive Enterprise Simulator , Incisive , metric-driven verification , MDV , Incisive Enterprise Simulator (IES)

Breakfast Bytes

Marie Pistilli Passed Away

Marie Pistilli, who was injured in a car-crash in October (as I included in my first…

• less than a min read
CDNS - Fix Layout Hompage