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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Breakfast Bytes

JasperGold: Stepping up to RTL Signoff

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon…

• 7 min read
Intel , Jasper , JasperGold , Formal verification

Breakfast Bytes

The New Tensilica Fusion G6 DSP

Only last week, in Are General-Purpose Microprocessors Over? I wrote about how general…

• 4 min read
fusion G6 , Tensilica , Breakfast Bytes , digital signal processor

Computational Fluid Dynamics

Fluid Dynamics Simulation of a Generic Gas Turbine Combustor

This case study on combustion and radiative heat transfer in a generic gas turbine…

• less than a min read

Breakfast Bytes

FD-SOI State of the Union: There's Supply—Is There Demand?

I went to the annual SOI Silicon Valley Symposium recently. As last year, they had…

• 11 min read
dreamchip , China , NXP , 22fdx , 12fdx , Samsung , handel jones , GlobalFoundries , ARM , ibs , Breakfast Bytes , FD-SOI

Analog/Custom Design

Virtuosity: What's New in analogLib

It's been a while since analogLib was updated, so we decided to pay some attention…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , ADE , Virtuoso , Analog Design Environment , Schematic Editor , Virtuosity , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

RISC-V 6th Workshop 上海

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai…

• 11 min read
computer architecture , risc-v , risc-v foundation , dave patterson

Breakfast Bytes

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

• less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Breakfast Bytes

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

• 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - CNN Challenges: Compute Requirement

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

• 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

Breakfast Bytes

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

• 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

Breakfast Bytes

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

• 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: How Can I Plot or Evaluate with the New Expression Builder…

Indeed, the new Expression Builder has made expression creation much easier, but…

• 3 min read
Analog Design Environment , evaluateADE Explorer , Analog Simulation , plot , expressions , analog , Mixed-Signal , Expression Builder , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

• 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

• less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

• 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

• less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN

Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

• 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Digital Design

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS
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