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業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Computational Fluid Dynamics

Assumptions and Insights of k-epsilon Low Re Yang-Shih Turbulence Model

Key Takeaways A new time scale-based k-epsilon (k-ɛ) model for near-wall turbulence…

• 7 min read

SoC and IP

Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet…

• 4 min read
ucie , IP , die-to-die

System, PCB, & Package Design 

Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges

Power network design and analysis of 3D-ICs is a major challenge due to the complex…

• 4 min read
PDN , 3D-IC , Integrity , Power Integrity , in-design analysis , Sigrity , Clarity 3D Solver

Life at Cadence

Creating Connections through Career Catalyst

Early career employees Ankit Narasimhan, Jai Ganesh Iyer, Jhenkar Kallambella Suresh…

• 4 min read
Insights on Culture , Culture , my life at cadence , life at cadence

Corporate News

First Major Toolbox for MATLAB/Simulink Model Deployment to Tensilica HiFi DSPs

Traditionally, developing software for digital signal processors (DSPs) involves…

• 3 min read
featured , Tensilica

Data Center

Tradeoffs in Managing Data Center External Airflow

By Matthew Kaufeler, Senior Principal Product Engineer When you build a data center…

• 4 min read

Verification

Partial Header Encryption in Integrity and Data Encryption for PCIe

Cadence PCIe/CXL VIP support for Partial Header Encryption in Integrity and Data…

• 3 min read
CXL , Verification IP , PCIe , IDE

Learning and Support

Accessing Doctype Definitions in the Cadence Learning and Support Portal – pt 2

Hopefully, our blog Doctype definition and accessing them on Cadence Learning and…

• 2 min read

Computational Fluid Dynamics

Deciphering the Potential of High-Fidelity CFD Simulations Across Industries

The landscape of CFD is undergoing a novel shift with the emergence and application…

• 5 min read
CFD , Automotive , Aerospace , Millennium M1 , Fidelity CFD , simulation software , LES

Data Center

CadenceCONNECT: Take the Heat Out of Your AI Data Center

As we delve deeper into the AI era, data centers have become the backbone of technological…

• 1 min read

Corporate News

International Women in AI Day: Creating More Opportunities for Women in AI

In the rapidly evolving world of artificial intelligence (AI), diversity is not just…

• 3 min read
Cadence Giving Foundation , featured , Cadence Cares , Women in AI , International Women in AI Day , gender equity , Women in AI Month , Fem.AI , AI , Women in AI Day , Women in Technology

Analog/Custom Design

Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer Part 3

Welcome back to the Doc Assistant A-Z blog series! Since the launch of Doc Assistant…

• 3 min read
In-Tool Help , user documentation , in-built help , Cloud-Based Help , Doc Assistant

Analog/Custom Design

Spectre 24.1 Release Now Available

The SPECTRE 24.1 release is now available for download at Cadence Downloads. For…

• 5 min read
Spectre 24.1 , RF Library , spectre aps , Spectre X EMIR , Spectre RF , fitting tool , Spectre Circuit Simulator , S-Parameter Quality Checking tool , Spectre , Spectre Fast Monte Carlo , spectre x , Spectre X Simulator

SoC and IP

Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

Today's high-performance computing systems often require the designer to instantiate…

• 4 min read
AXI , Tensilica , Xtensa , FPGA

Verification

Jasper Formal Fundamentals 2403 Course for Starting Formal Verification

The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those…

• 2 min read
Jasper Formal Fundamentals , FPV , Formal Analysis , formal , Jasper , Jasper Apps , Formal verification , verification

Computational Fluid Dynamics

Highlights from the CadenceLIVE India CFD Track

On September 13, CadenceLIVE India marked its second successful year in the computational…

• 2 min read
CFD , featured , Beta CAE , Celsius EC Solver , Fidelity CFD , cadencelive , Customer Presentations

System, PCB, & Package Design 

10 Most Viewed Posts in Cadence Community Forum

Community engagement is a dynamic concept that does not adhere to a singular, universal…

• 2 min read
PCB , CFD , Allegro X AI , Community , cadence , awr , community forum , PCB Editor , OrCAD , PCB design , OrCAD X , allegro x , PCB Capture

Corporate News

Transforming Drug Discovery with Computational Methods

The recent pandemic has highlighted the critical need for rapid and cost-efficient…

• 6 min read
drug discovery , biosimulation , computational software , biomedical , openeye , orion , AI

Verification

DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM)

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application…

• 3 min read
Verification IP , DDR5 SDRAM , DDR5 UDIMM , VIP , JEDEC , DRAM , DDR5 CUDIMM , memory models , DDR5 SODIMM , DDR5DIMM
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