Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Mark Papermaster: Moore's Law Plus

Recently, I wrote about Robert Lang's presentation on Computational Origami . He…

• 4 min read
epyc , has , chiplets , rocm , AMD , 3DIC , 2.5D IC , Breakfast Bytes

Breakfast Bytes

How to Build and Connect a Trillion Things: Arm TechCon Preview

Rob Aitken is digging a bit deeper into what it would really take to connect a trillion…

• 7 min read
security , ARM Techcon , trust , IoT , Internet of Things , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - What's Driving Automotive Memory Trends and Technologies…

In this week's Whiteboard Wednesdays, the second in a three-part series, Scott Jacobson…

• less than a min read
Automotive , Whiteboard Wednesdays , automotive electronics , ADAS , memory models

The India Circuit

Have an e-Cracker of a Diwali!

Diwali is finally here! One of India’s most favorite festivals, it is celebrated…

• 2 min read
e-cracker , firecrackers , Cadence India , Diwali , e-pataka

Verification

Munich October 18—Come See SystemC Evolution Day!

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to…

• 2 min read
Munich , Functional Verification , Accellera , SystemC , event

Breakfast Bytes

The Empire Long Divided Must Unite

Chinese children are familiar with the opening lines of Romance of the Three Kingdoms…

• 6 min read
organization , functional organization , corporate cad cycle , CEO , three envelopes , Breakfast Bytes

Learning and Support

One Click to Know About Your Product on Cadence Support

Like with any new product in market everyone is anxious about knowing all the features…

• 1 min read
COS , New Release , Cadence Online Support , Support , product

Verification

Mediatek Deploys Perspec for SoC Verification of Low Power Management (part 3 of…

Here we conclude the blog series and highlight the results of Mediatek 's use of…

• 1 min read
uvm , Perspec , coherent , perspec system verifier , coherency library , coherency , Accellera , mediatek , ARM , pss , portable stimulus

Breakfast Bytes

Are We There Yet? Metric-Driven Signoff

Are we there yet? All verification suffers from the problem of trying to decide when…

• 4 min read
CDNLive , Metric Driven Verification , ST Microelectronics , MDV , simulation , Breakfast Bytes , vManager , verification

Analog/Custom Design

The Art of Analog Design Part 4: Mismatch Analysis

In Part 3 , we started to explore how to analyze the results of Monte Carlo analysis…

• 3 min read
spectre aps , Analog Design Environment , Virtuoso Variation Option , mismatch analysis , Analog Simulation , Monte Carlo , Custom IC Design

Analog/Custom Design

The Art of Analog Design Part 5: Mismatch Analysis II

In Part 4 of the series, we looked at applying mismatch analysis as a design tool…

• 3 min read
spectre aps , offset voltage , mismatch analysis , Analog Simulation , ADE , Monte Carlo analysis , Strong Arm latch , dynamic comparator

Verification

Teradyne Standardizes on Xcelium Simulator

Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator…

• less than a min read
Teradyne , ASIC , press release , xcelium , JasperGold , vManager

Verification

Teradyne "Formally" Adopts JasperGold FPV

CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation…

• 2 min read
Teradyne , FPV , CDNLive , customer success , JasperGold , Formal verification

Analog/Custom Design

Virtuosity: Can I Speed up My Plots?

If your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® ADE XL setup…

• 3 min read
Analog Design Environment , ADE GXL , ADE Explorer , Explorer , ADE XL , analog , license , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuosity , mixed signal , Custom IC Design , ADE Assembler

Breakfast Bytes

Rowen on Vision, Innovation, and the Deep Learning Explosion

The keynote for the second day of the Linley Processor Conference was by Chris Rowen…

• 5 min read
Chris Rowen , deep learning , linley processor conference , deeplearningmachinelearning , Computer Vision , Tensilica , vision , neural networks , Breakfast Bytes

Verification

Celebrating Five Years of Performance-Optimized Arm-Based SoCs: Now including AM…

It’s been quite a long 5-year journey building and deploying Performance Analysis…

• 2 min read
iwb , interconnect , amba5 , Interconnect Workbench , Palladium , Performance Analysis , AMBA , CoreLink , xcelium , ARM

Computational Fluid Dynamics

Aerodynamic Simulation of a NASA Common Research Model (CRM) Aircraft for JAXA APC…

Born through the merger of three previously independent organizations on October…

• 5 min read

Breakfast Bytes

Linley Gwennap on the Microprocessor Market

Linley Gewennap always gives the opening keynote for the Linley Microprocessor Conference…

• 6 min read
Automotive , Intel , risc-v , linley processor conference , deeplearningmachinelearning , processor , AMD , linley group , IoT , Tensilica , Internet of Things , ADAS , ARM , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview October 16th to 20th 2017

https://youtu.be/CUabZn_-1_M Coming from a cartoon world (camera Sean) Monday…

• less than a min read
metric driven signoff , Metric Driven Verification , AMD , semi , vishal kapoor , sjsu , Jim Hogan , strategic materials conference , Oski , Formal verification
CDNS - Fix Layout Hompage