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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

SoC and IP

More free DAC exhibit tix; One more chance to win an Apple iPad

A bit more than a week ago, this blog carried the news that you could get a free…

• 1 min read

SoC and IP

Samsung announces imminent release of a multichip module integrating DRAM and PCM…

Hot on the heels of Numonyx’ announcement of two commercial PCM (phase-change memory…

• 1 min read

Verification

See You at CDNLive! EMEA

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big…

• 2 min read
CDNLive!ive! , System Design and Verification

Verification

2010 CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive…

• 2 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

Verification

Team Verify's 2010 CDNLive Munich Guide

We're excited to report that next week's annual CDNLive! event in Munich will feature…

• 1 min read
ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Contributions , SVA , PSL , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About APD’s Super Smooth Routing? See for yourself in the SPB16.3 Release

When using the point-to-point routing in the packaging products ( APD and SIP ),…

• 3 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , IC Packaging , Allegro 16.3 , SPB 16.3 , APD , advanced package designer , PCB design , Allegro PCB Editor , Cline change

Verification

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL

SoC and IP

NAND Flash as the media killer: Sony to kill the floppy in Japan, finally

Sometimes it takes decades but NAND Flash semiconductor memory is turning out to…

• 1 min read

System, PCB, & Package Design 

Favorite Features of an IC Package Designer: Flexible 3D Viewing

This is the first in a series of discussions we would like to open up regarding…

• 1 min read
SiP , Digital SiP design , 3D-IC , Allegro 16.3 , TSV , APD , IC Packaging & SiP design , IC Package Physical layout and co-design , Kulicke & Soffa

Verification

Verified by e/Specman: The Palladium XP Verification Computing Platform

After much anticipation, it feels great to be free to proclaim that e /Specman (as…

• less than a min read
metric driven verification (MDV) , Functional Verification , e , Palladium XP , MDV , IES-XL

SoC and IP

Corsair Video vividly shows SSD speedup on laptop

Wondering whether an SSD really makes that much difference to laptop performance…

• less than a min read

Digital Design

Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

In the past number of weeks/months we have all seen how Toyota has struggled to manage…

• 2 min read
toyota , Digital Implementation , BMW , microprocessor , verification

Verification

Ubuntu on ARM is Growing

Based on the title, you probably guessed I'm talking about growing in popularity…

• 6 min read
virtual platform , System Design & Verification , Embedded Linux , QEMU

System, PCB, & Package Design 

Who’s up for Chinese?

Recently, someone asked me " .. . why bother translating OrCAD products to Chinese…

• 1 min read
Capture CIS' , PSPICE , OrCAD , PCB design , PCB Capture , Schematic

SoC and IP

What is a Flash cache?

A Flash cache acts like SRAM memory caches that are designed to speed up DRAM access…

• 3 min read

SoC and IP

Free DAC Tix -- Better hurry ‘cause they’re going fast

Love DAC? Design chips? Looking for a job? Today’s your lucky day. Denali, Atrenta…

• 1 min read

SoC and IP

Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available…

Numonyx has announced or reannounced two 128-Mbit non-volatilve memory devices based…

• 2 min read

System, PCB, & Package Design 

What's Good About Simplifying the Use of Third-Party SI Models? It's in SPB16.3!

Today, many users receive SI models that are not in DML format. They are given IBIS…

• 8 min read
PCB SI , SI , HSPICE , Signal Intregrity , IBIS , SigXP UI , PCB Signal and power integrity , SPB 16.3 , IBIS-AMI , PCB design

Verification

UVM Based on OVM 2.1.1: What a Great Idea!

Regular readers know that I have been urging the Accellera VIP TSC to base its Universal…

• 2 min read
uvm , Verification methodology , OVM , Functional Verification' signal integrity , Contributions , Accellera
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