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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Digital Design

Five-Minute Tutorial: Why You Should Be Running Early DRC

Everyone knows you have to run signoff DRC before you tape out a design. Sometimes…

• 3 min read
EDI , IP , routing access , filler , power grid , DRC , early DRC , endcap , encounter digital implementation system , NanoRoute , welltap , Verify Geometry , metal fill , signoff , macros , memories

Verification

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Every SoC project uses multiple languages. Even if the design itself is purely Verilog…

• 1 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , Functional Verification , OVM , e , webinar , UVM ML , multi-language , Accellera , SystemC , multi-language UVM , IES , IES-XL

Verification

Recorded Webinar: Using Metric-Driven Verification and Formal Together For Higher…

[Preface: the upcoming " Club Formal " on October 17 here at the Cadence San Jose…

• 3 min read
coverage , Functional Verification , Metric Driven Verification , Formal Analysis , formal , Incisive , webinar , Incisive Enterprise Verifier , Chris Komar , enriched metrics , MDV , IEV , debugging , John Brennan , simulation , Formal verification , IFV

Verification

Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their…

• 3 min read
AF , indexed ports , SystemVerilog , stub files , Specman , stubless indexed ports , Functional Verification , ports , Nir Hadaya , SV , e language , interface , simulation , Avi Farjoun

System, PCB, & Package Design 

Customer Support Recommended – Working with PADS to Allegro PCB Editor Translato…

A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor…

• 3 min read
COS , PCB , PADS translator , customer support , PADS , PADS to Allegro , Appnote , PCB design , Allegro PCB Editor , application note , Allegro

System, PCB, & Package Design 

What's Good About DEHDL’s Page Search? The Secret's in the 16.5 Release!

Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL…

• 1 min read
DEHDL find , page search , hierarchy , DEHDL , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Find result , Front-end PCB design , design , PCB design , Design Entry , Grzenia , SPB16.5 , ConceptHDL , Schematic , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Static IR Drop Analysis? 16.5 Has Many New Enhancements

In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into…

• 3 min read
PCB SI , PI , PCB PI , PDN , IBIS , SigXP UI , Power Integrity , "PCB SI" , High Speed , Allegro 16.5 , IBIS-AMI , SPB , design , Allegro PCB SI , 16.5 , "PCB PI" , Grzenia , SPB16.5 , SI analysis and modeling , IR drop , power , 3D viewer , Allegro

Analog/Custom Design

ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of…

• 2 min read
DAC , microcontrollers , Demo , Cortex-M , MCUs , Virtuoso , Cortex-M0 , incyte , fuel injection system , System Design Kit , micro-controllers , ARM , Balasubramanian

System, PCB, & Package Design 

What's Good About Allegro PCB Editor PDF Publisher? See for Yourself in 16.5!

Starting with release 16.5, it is possible to export data from Allegro PCB Editor…

• 2 min read
PCB , PCB Layout and routing , Allegro GUI , PDF , artwork , property , Allegro 16.5 , SPB , PDF Publisher , PCB Editor , Layout , design , PCB design , Grzenia , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17

Please join Team Verify and other design and verification engineers at the next …

• 1 min read
ABV , Formal Analysis , formal , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , Club Formal

Verification

iPhone5 Differentiation is Chip Design

In case you may have missed it, Apple recently launched a new iPhone. As per the…

• 5 min read
High-Level Synthesis , Apple , TLM , RTL , android , iPhone5 , Samsung , SoC , C-to-Silicon , software , smartphones , ARM , ESL , iPhone , Audience

Verification

Using a Network File System with the Xilinx Zynq-7000 Virtual Platform

There are a number of ways to do embedded software development for Xilinx Zynq-7000…

• 5 min read
Ubuntu 12.04 , Zynq virtual platform , Network File System , Embedded Linux

Analog/Custom Design

SKILL for the Skilled: Part 3, Many Ways to Sum a List

In Part 1 and Part 2 of this series of posts, I showed a couple of ways to sum up…

• 4 min read
recursive functions , Team SKILL , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , Custom IC Design , SKILL++

Verification

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

• 2 min read
validation. , Driver , firmware , System Design & Verification

Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

• 3 min read
uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

• 1 min read
PCB , data management , symbol editor , flow manager , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , Library and design data management , SPB , Design Entry HDL , design data management , symbol , design , PCB design , Design Entry , Grzenia , SPB16.5 , Librarians , library , ADW , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

• 4 min read
Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Digital Design

Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI…

• 4 min read
EDI , DRC , design rules , DRC signoff , LEF , Cadence Online Support , NanoRoute , encounter , Digital Implementation , Encounter Digital Implementation , Verify Geometry , PVS , DRC violations , debug DRC violations

Analog/Custom Design

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

• 3 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design
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