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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in…

• 2 min read
System Design and Verification , SoC , Semiconductor , ESL

Analog/Custom Design

Exceed On Demand And Virtuoso IC6.1

Many of our customers use our Virtuoso software in combination with the windows…

• less than a min read
IC 6.1 , OpenText , Exceed on Demand , Virtuoso , Cusstom IC Design

System, PCB, & Package Design 

What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen

This week, I'm taking a brief break from the usual PCB solution/product technical…

• 2 min read
Optical Wiring , OPCB , PCB Editor , PCB design , Allegro

Verification

Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group…

• 3 min read
Specman , debug , Functional Verification , e , Funcional Verification , Aspect Oriented Programming , AOP

Verification

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Verification

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

System, PCB, & Package Design 

What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PCB design , Allegro

Digital Design

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Effi…

Digital designs are reaching 10's of millions of instances, which makes efficiency…

• 2 min read
timing system , dynamic rail analysis , Static timing analysis , Early Rail Analysis , Multi-Core and Parallel rocessing , Statistical , Extraction , Signoff Analysis , timing constraints , SI analysis , noise analysis , OCV , Signal Integrity , Digital Implementation , Timing analysis , Power Analysis , signoff , timing convergence

Analog/Custom Design

Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements

I'm not going to beat around the bush here. I could tell you about all the things…

• 2 min read
Virtuoso Analog Design Environment , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing…

• 1 min read
metric driven verification (MDV) , Functional Verification , vPlan , Cadence VIP portfolio , OVM , VIP , Compliance Management System , CMS , AMBA , ARM

Verification

Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and…

• 2 min read
SystemVerilog , Specman , Testbench simulation , e , verification

Verification

Running Incisive on Ubuntu Linux

Ubuntu is by many accounts the most popular and the easiest to use Linux distribution…

• 4 min read
Incisive , Ubuntu , Systemm Design and Verification , Virtual Machine , linux

System, PCB, & Package Design 

What's Good About Capture’s Auto-Wiring? You’ll Need The SPB16.3 Release to See!

Just a brief post this week to highlight one of the new SPB16.3 features in Allegro…

• 3 min read
Design Entry CIS , SPB 16.3 , Auto-wire , PCB design , Allegro

Verification

Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a…

• less than a min read
Object Oriented Programming , Functional Verification , e , DVcon , OOP , Aspect Oriented Programming , AOP

Analog/Custom Design

Things You Didn't Know About Virtuoso: Thumbnails

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence…

• 1 min read
IC 6.1 , thumbnails , Virtuoso , IC 6.1.4 , Custom IC Design

Analog/Custom Design

Analog Behavioral Modeling - What Language Do You Speak?

An increasing number of mixed-signal design teams are contemplating adding analog…

• 2 min read
mixed-signal simulators , MMSIM , analog , Mixed-Signal , Block-level simulation , AMS simulation , Circuit Design , mixed signal , Custom IC Design , Custim IC Design , Cusstom IC Design

Verification

DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010…

• less than a min read
Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , DVcon , OOP , AMIQ , OVM SC

Verification

DVCon 2010 Rocked!

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010 , and…

• 1 min read
DAC , uvm , methodology , Functional Verification , OVM , DVcon

Verification

DVCon 2010 - Day 2

Click here or on the image below to go to the annotated photo blog of DVCon Day 2…

• less than a min read
Functional Verification , OVM , OVM e , CDV , OVM SV , e , Mike Stellfox , DVcon , OOP , AOP
CDNS - Fix Layout Hompage