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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

DVCon 2010 For The Specmaniac

At next week's DVCon in San Jose, CA, Cadence will cover all aspects of our verification…

• 4 min read
SystemVerilog , Specman , TLM , Object Oriented Programming , OVM ML , Functional Verification , OVM , OVM e , Incisive , e , Mike Stellfox , DVcon , OOP , AMIQ , SystemC , MDV , eRM , AOP , IES-XL

System, PCB, & Package Design 

Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

IBIS is sometimes known as the bird of knowledge, but is also the popular standard…

• 1 min read
PCB , SigXP UI , PCB Signal and power integrity , SPB 16.3 , IBIS-AMI , SerDes , PCB design

System, PCB, & Package Design 

What's Good About ASA Schematics? Numerous Improvements in The SPB16.3 Release!

Allegro System Architect (ASA) also known as System Connectivity Manager (SCM) allows…

• 1 min read
SCM , SPB 16.3 , Allegro 16.2 , ASA , PCB design , Schematic

Verification

Beyond Coverage: Adding Arbitrary Metrics To Your Metric-Driven flow

The most common metrics used in current metric driven verification (MDV) flows are…

• 3 min read
Specman , metric driven verification (MDV) , Functional Verification , vPlan , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES-XL

Verification

Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be…

• 4 min read
High-Level Synthesis , Verification planning and management , TLM-driven design , TLM , System Design and Verification , embedded software , virtual protoype , ESL handoff , SystemC , C-to-Silicon Compiler , TLM 2.0-driven design , verification

Verification

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week…

• 2 min read
Specman , Funcional Verification , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Font Support? The Secret's in The SPB16.3 Release!

Well - it's here! Native font support in Allegro Design Entry HDL (DEHDL)! This has…

• 8 min read
DEHDL , SPB 16.3 , Allegroro , PCB design , Design Entry , File Directives

SoC and IP

What’s on the Horizon for NAND and DRAM?

Young Choi , Guest Blog for Denali Software January is a time where lots of…

• 4 min read

Verification

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology…

Cadence is in the vanguard of a movement to a higher level of productivity via the…

• 3 min read
TLM , RTL , System Design and Verification , IP re-use , Synthesis , verification

Digital Design

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

• 1 min read
Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

System, PCB, & Package Design 

Come See TeamAllegro at DesignCon2010

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC…

• 1 min read
SiP , Signal Intregrity , Allegro 16.3 , IBIS-AMI , PCB design , Desigcon

Verification

How Big Is An int?

This week I'm taking a break from my series on Android System Verification to talk…

• 8 min read
Small Device C Compiler , wishbone , z80 , OpenCores , ISX

Verification

Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend…

• 1 min read
Functional Verification , CPF , Low-Power , UPF , SystemC , IES , ESL

Verification

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

System, PCB, & Package Design 

What's Good About SiP Layout ADRC? See For Yourself Using The SPB16.3 Release!

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User…

• 16 min read
SiP , DRC , SPB 16.3 , ACSET , ADRC , PCB design

Verification

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Methodology Is Important But Language Matters - Part 1

Historical trends in languagesMany of us have traveled around the world, and while…

• 3 min read
Verification planning and management , TLM , virtual platform , System Design and Verification , ESL High Level Synthesis , OVM , ASIC/ASSP , ANSI-C , C-to-Silicon , virtual prototype , C program , OSCiI , TLM 2.0-driven design , planning and management , ESL

SoC and IP

The Evolving Enterprise SSD: Gartner’s Forecasts

By Steve Leibson for Denali Software The appearance of SSDs into the storage…

• 5 min read
CDNS - Fix Layout Hompage