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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

Verification

The Scoop on the New Incisive Enterprise Verifier

Last week we announced Incisive Enterprise Verifier (IEV). What is cool about IEV…

• less than a min read
funtional verification , ABV , CDNLive , Functional Verification , Formal Analysis , Testbench simulation , Incisive , Incisive Enterprise Simulator (IES) , verification

Verification

Webcast: EDA, ESL and More Ideas From DAC

From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled…

• less than a min read
System Design and Verification , PMC Sierra , OpenSystems , Virtual Platforms , ISX , ESL

Verification

Virtualization and Simulation Roundtable

A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena…

• 2 min read
virtualization , VMware , Palladium , Virtual Box , EDA Cafe , ARM , System Design and Verification

Verification

Spanning the Globe to Bring You the Constant Variety of Verification

Any sports fan living in the US during the 70's and 80's will remember the dramatic…

• 3 min read
events , Specman , Object Oriented Programming , CDNLive , Functional Verification , OVM , OVM e , EDA , Incisive , team specman , OOP , Twitter , ClubT , AOP , Trailblazer

Verification

UPDATE: EU ClubT's Start This Week!

Just a quick reminder that the ClubT series starts this week! Here are the specific…

• 2 min read
IEEE 1647 , events , IntelliGen , Low Power , Specman , HW/SW , TLM , OVM ML , metric driven verification (MDV) , Functional Verification , OVM , VIP , OVM e , Mixed Signal Verification , Incisive , e , Enterprise Manager , ISX (Incisive Software Extensions) , ClubT , SystemC , MDV , ESL , IES-XL , Trailblazer

Digital Design

Leakage Power and National Security

I read an interesting article recently on EDN regarding a new way to determine cryptographic…

• 1 min read
Palladium DPA , leakage , Digital Implementation , power

System, PCB, & Package Design 

What's Good About PDV Symbol Property Templates? The Secret's in the SPB16.2 Release

Allegro PCB Librarian / Part Developer (PDV) Symbol Property Templates have been…

• 2 min read
SPB 16.2 , PDV Symbol , templates , property , PCB design , Allegro

Digital Design

Running Low on Power or Receiving Mixed Signals? Talk to the Expert Users

Everytime my wife and I are looking to buy a big item, we do our research by reading…

• 1 min read
Mixed-Signal , Logic Design , Digital Implementation , mixed signal , verification

Verification

Intrusive Software Debugging: Friend or Foe?

One of the great benefits of working with simulation (RTL, SystemC , or any Virtual…

• 4 min read
virtual platform , System Design and Verification , Co-verification , SystemC , TLM 2.0 Trace , debugging

Verification

Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself…

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all…

• 1 min read
PMCS , TLM , IBM , System Design and Verification , Vittuatech , DAC&V , CoWare , C-to-Silicon , SystemC , CDNLive! , ARM , TI

System, PCB, & Package Design 

What's Good About APD's Design Integrity Check? - It's in SPB16.2!

The Cadence IC Packaging tools are complex, flexible tools that allow a designer…

• 4 min read
SPB 16.2 , Integrity Check , IC Packaging , APD , Allegro 16.2 , PCB design

Verification

The Power of Parallel Thinking: Multi-Core Cadence

A while back, as we were preparing to launch our first phase of multi-core support…

• 1 min read
Functional Verification , Formal Analysis , Testbench simulation , Multi-Core , verification

Verification

Using Vera is like Speaking Sumerian – Who’s Left to Understand?

Just like natural languages, non-standard verification languages can fade away.…

• 1 min read
SystemVerilog , Vera , Functional Verification , OVM , e , IES , RVM , VMM

Verification

Verification is a Sprint and a Marathon!

Verification engineers have updated an old adage to discribe their projects: Verification…

• 1 min read
performance , SystemVerilog , Functional Verification , OVM , Low-Power , Multi-Core , Incisive , Simulation acceleration , IES

Verification

CDNLive San Jose 2009 for the Specmaniac

Even sooner than the EU ClubTs is CDNLive San Jose 2009 , where this year the event…

• 3 min read
SystemVerilog , Low Power , Specman , HW/SW , CDNLive , OVM ML , metric driven verification (MDV) , Functional Verification , OVM , VIP , MDV techtorial , OVM e Enterprise Planner , Multi-domain verification: HW/SW co-verification , Incisive , OVM SV , e , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , multi-language , ClubT , SystemC , eRM , ESL , OVM SC , Coverage Driven Verification , IES-XL

Verification

EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back…

• 2 min read
IEEE 1647 , events , IntelliGen , Low Power , Specman , HW/SW , OVM ML , metric driven verification (MDV) , Functional Verification , OVM , VIP , OVM e , Mixed Signal Verification , Multi-domain verification: HW/SW co-verification , Incisive , e , ISX (Incisive Software Extensions) , ClubT , SystemC , ESL , IES-XL , Trailblazer

Verification

Must Have Advanced Verification to Achieve Software Signoff

In a recent blog on EDA Graffiti, Paul McClellan he talks about Software Signoff…

• 2 min read
EDA Graffiti , System Design and Verification , embedded isx , software signoff

Verification

Specman 9.2 Preview: A Fresh Profile on the Profiler

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 2 min read
performance , Specman , Functional Verification , e , team specman , IES-XL

Verification

Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip…

I'm not proud to admit that I reacted with envy to the news that Twitter just received…

• 2 min read
events , Specman , CDNLive , metric driven verification (MDV) , Functional Verification , IBM , VIP , MDV techtorial , DVClub , Enterprise Manager , Enterprise Planner , team specman , DVcon , Twitter , ARM , MDV , verification , Trailblazer
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