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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Verification

New Video on "Metric Driven Verification 101", With Yours Truly Giving the Intro

Recently I had the honor of delivering the introductory section of a detailed demo…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Coverage-Driven Verification , Enterprise Manager

Verification

Tip for Linking AMIQ’s DVT to the Specman Docs

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development…

• 2 min read
Specman , Tech Pubs , Functional Verification , tech tips , Incisive , AMIQ , Incisive Enterprise Simulator (IES) , IES-XL

System, PCB, & Package Design 

What's Good About the new FPGA System Planner? - Ask Hemant Shah!

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the…

• 2 min read
FPGA System Planner , FSP , PCB design , FPGA

Verification

OVM Metric Driven Verification With an FPGA-based Design

During the last 2 years I have enjoyed the opportunity to work with the Incisive…

• 2 min read
System Design and Verification , OVM , Incisive , System simulation and analysis , ISX , Hardware/software co-verification , FPGA

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 2

I keep my toothpaste in my bathroom. I keep the paprika in the kitchen. I keep the…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

The DWARF Debugging File Format

The Chronicles of Narnia has always been one my favorite series of books. Today,…

• 7 min read
System Design and Verification , DWARF , ARM , ELF , debugging

Verification

Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work…

• 5 min read
SystemVerilog , debug , Functional Verification , simvision , OVM SV , OVM 2.0 , IES , IES-XL

Verification

Team genIES Bloggers Create Simulation Magic

Simulation is a huge topic. Performance, debug, mixed-signal, low-power, assertions…

• 1 min read
Functional Verification , Incisive , OV , IES , IES-XL

Verification

Tips on Using “vhdlsync” With e+Mixed HDL Simulation

[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share…

• 3 min read
AF , Specman , Functional Verification , tech tips , Incisive , e , Verilog , multi-language , Incisive Enterprise Simulator (IES) , VHDL , IES , IES-XL

Verification

Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

As noted in a prior post , I had the pleasure of attending a DVClub talk given by…

• 2 min read
verification strategy , metric driven verification (MDV) , Functional Verification , DVClub , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 1

Yeah, right...in this economy, don't talk to me about real estate. But I'm not talking…

• 3 min read
real estate , Virtuoso , assistants , Custom IC Design

Verification

Heads-up: Mixed Signal Verification Webinar (June 10)

For those Specmaniacs using the REAL number data type & ports capabilities in Specman…

• 1 min read
AMS , Specman , verification strategy , Functional Verification , Incisive , e , Incisive Enterprise Simulator (IES) , verification , IES-XL

RF Engineering

Join us at the Cadence booth at the International Microwave Symposium

If you listened to Tom's advice on this blog two months ago and registered for the…

• 1 min read
RFIC , Spectre RF , Virtuoso , RF design , International Microwave Symposium

Verification

New IntelliGen Statistics Collection Utilility

As noted in white papers , prior posts , and the Specman documentation, since IntelliGen…

• less than a min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , Incisive , e , team specman , Incisive Enterprise Simulator (IES) , IES , IES-XL

Verification

Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, …

• 2 min read
System Design and Verification , rtl compiler , C-to-Silicon Compiler

Analog/Custom Design

Things You Didn't Know About Virtuoso: Editing Properties

When I was growing up, my mother would usually bake a ham for Christmas dinner. She…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Digital Design

MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways…

• 2 min read
EDI , EDI system , encounter digital implementation system , Digital Implementation

SoC and IP

The Great Escape, Part II: How These Companies Exited the DRAM Business

Case Histories of Significant DRAM Market Withdrawals : This article continues…

• 18 min read

Verification

Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all…

• 1 min read
Functional Verification , charity benefit , Stars and Strikes festival
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