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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About New Smoke Analysis Devices? Check out the SPB16.2 Release and See

The AMS Simulator Smoke Analysis has been enhanced in the SPB16.2 release to support…

• 2 min read
SPB 16.2 , AMS simulator , Smoke Analysis , PCB design , model editor

Verification

ISX Presentations at CDNLive! Munich

As we head into next weeks CDNLive! event in Munich it's great to see today's post…

• 1 min read
cdnlive! emea 2009 , System Design and Verification , ISX

SoC and IP

Taiwan: From Death by DRAMs to Finding Foundry Success

Vanguard International Semiconductor, Once a DRAM failure, is Now a Successful Junior…

• 7 min read

SoC and IP

Taiwan DRAM Makers...Trapped by Their Culture?

Can Taiwanese DRAM Makers Decide What to do Next...in Time? We recently saw…

• 3 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Introduction

A while ago, I somehow ended up on the mailing list of a rather odd catalog called…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

IEEE P1647-2010 Call For Participation

Attention Specmaniacs: the IEEE 1647 working group is looking for a few additional…

• 2 min read
IEEE 1647 , Specman , Functional Verification' signal integrity , OVM e , e , OVM-e , eRM , AOP

Verification

CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 18-20 is the annual…

• 3 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

SoC and IP

Cross Currents in Memory Market Signal Changes Ahead

No one can say with any certainty, but... Recent improvements in DRAM and NAND…

• 6 min read

Verification

Modeling Interfaces with C-to-Silicon Compiler

Users of ESL tools are curious about the procedure for handling the interface to…

• 2 min read
CTOS , System Design and Verification , TLM 2.0 , SystemC analysis , C-to-Silicon , transaction level modeling , high level synthesis , Modeling , HLS , dma

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 3

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM…

• 7 min read
TLM , simvision , System Design & Verification , ESL

Verification

e Coding Made Easy with the “DVT” Integrated Development Environment

Specmaniacs everywhere should be aware of a great, full-featured integrated development…

• 6 min read
IEEE 1647 , SystemVerilog , eclipse , Specman , CDNLive , Functional Verification , OVM , OVM e , OVM SV , e , specman elite , AMIQ , eRM

Verification

It's Not Too Early to Think About DAC 2009

Even though it's still a couple of months off, it's not too early to think about…

• 1 min read
DAC 2009 , System Design and Verification , hardware-dependent software

Verification

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Analog/Custom Design

Jurassic Park IV: The Return of ANALOG

In the lab, no one can hear you scream! When I was getting my BSEE in the…

• 2 min read
analog , Incisive , encounter , Virtuoso , RF design , Custom IC Design

Digital Design

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Digital Design

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Analog/Custom Design

An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso…

The emergence of sub-micron technologies has enabled today’s designers to include…

• 1 min read
CDNLive , Virtuoso , Spectre , RF design , MDL

Verification

Using Macros for Repetitive Coding Tasks

For this post welcome guest blogger Hilmar van der Kooij. Hilmar is a Cadence Application…

• 5 min read
Specman , Functional Verification , tech tips , OVM , OVM e , Coverage-Driven Verification , team specman , Aspect Oriented Programming , macros , AOP

SoC and IP

Early Returns on 1Q09 Financials

Memory Companies Suffer More in 1Q09, but Future Looks Better...or so they say: …

• 4 min read
CDNS - Fix Layout Hompage