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Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
Reela Samuel 2 Sep 2025 • 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

SoC and IP

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

tomhackett 23 Feb 2018 • 4 min read
Galileo , GPS , IoT , Tensilica DSPs

Breakfast Bytes

How Do You Get to Be CEO?

I wrote last week about Being CEO and I said that I'd done it twice in my career…

Paul McLellan 23 Feb 2018 • 6 min read
board , management , chief executive officer , leadership , CEO

Analog/Custom Design

Virtuosity: New Eye Diagram Measurements

The Eye Diagram assistant in Virtuoso Visualization and Analysis allows you to create…

Arja H 23 Feb 2018 • 2 min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Verification

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

DimitryP 22 Feb 2018 • 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2018

https://youtu.be/wq86edcqTdw Coming from Building 10 lobby (camera Sean) Monday…

Paul McLellan 22 Feb 2018 • less than a min read
fec , patent , journalism , Embedded World , forward error correction

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (7 of 8)

Backchannel Training Another capability related to equalization adaptation is backchannel…

Sigrity 22 Feb 2018 • 2 min read
Serial link analysis , IBIS-AMI , PCIe , Signal Integrity , Backchannel , Sigrity

Breakfast Bytes

Paul Kocher: Differential Power Analysis and Spectre

Paul Kocher is a legend in security. A couple of weeks ago SiFive hosted a seminar…

Paul McLellan 22 Feb 2018 • 11 min read
security , risc-v , Spectre , Paul Kocher , sifive

Digital Design

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

dpursley 21 Feb 2018 • 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Breakfast Bytes

Is Big Brother Watching You?

I recently came across a fascinating piece by Paramal Satyal . He is Nepalese although…

Paul McLellan 21 Feb 2018 • 6 min read
security , cookie , webbkoll , advertising

Verification

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

XTeam 20 Feb 2018 • 1 min read
Functional Verification , DVcon 2018 , tutorials , event

Whiteboard Wednesdays

Whiteboard Wednesdays - Using DDR PHY Power Features to Reduce Power Dissipation

In this week's Whiteboard Wednesday video, Marc Greenberg explains the ways to optimize…

References4U 20 Feb 2018 • less than a min read
Whiteboard Wednesdays , DDR PHY , Low Power DDR

Breakfast Bytes

embedded world 2018 Preview

It's nearly time for embedded world 2018 (yes, it likes to be trendy and put it all…

Paul McLellan 20 Feb 2018 • 5 min read
Automotive , embedded world 2018 , 22fdx , Vision DSP , Tensilica , ADAS , GlobalFoundries

Breakfast Bytes

Why 1 Is Not a Prime Number

It's Presidents' Day and Cadence is on holiday. So time for me to write about something…

Paul McLellan 19 Feb 2018 • 6 min read
PI , fundamental theorem of algebra , fundamental theorem of arithmetic , tau , central dogma of biology

Breakfast Bytes

Suddenly You Are CEO. What Do You Do Next?

We've covered sales , marketing , and application engineering . Let's go up to the…

Paul McLellan 16 Feb 2018 • 7 min read
board , chief executive officer , CEO

Breakfast Bytes

What's For Breakfast? Video Preview February 19th to 23rd 2018

https://youtu.be/M3p1Luf4mtk Coming from Guangzhou, China (camera Carey Guo) Monday…

Paul McLellan 15 Feb 2018 • less than a min read
cookie , Spectre , Paul Kocher , CEO , Embedded World , 3rd party cookie

Breakfast Bytes

Zombies

What is a zombie? It depends on who you ask. Venture capitalists talk about zombies…

Paul McLellan 15 Feb 2018 • 8 min read
android , unix , iOS , zombie , linux , venture capital

Digital Design

Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose…

Philippe Hurat 14 Feb 2018 • 1 min read

Analog/Custom Design

Virtuoso Video Diary: Self-Paced Learning through Training Bytes

Cadence Education Services offers several online training courses and training bytes…

Uma Peethambaran 14 Feb 2018 • 4 min read
training bytes , Virtuoso , Virtuoso Video Diary , Virtuoso Layout

Academic Network

3rd Tensilica Day in Hanover: Extending our Senses

Two events in a row are a coincidence, three events are a series. With these words…

Anton Klotz 14 Feb 2018 • 2 min read
university , Hannover University , Cadence Academic Network , academic workshop , Tensilica
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