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Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

The webinar on “Effective system-level coverage” does an effective coverage of the…

If you're anything like I am, you listen to webinars with one ear, occasionally checking…

• 4 min read
system-level coverage , PXP , hardware assisted verification , webinar , Palladium XP , hardware acceleration , EDA webinar , hardware accelerated verification

System, PCB, & Package Design 

Customer Support Recommended – Using Test Points in Allegro Design Entry CIS and…

A test point is a location within an electronic circuit that is used to either monitor…

• 4 min read
Design Entry CIS , OrCAD Capture Marketplace , Capture CIS , PCB Editor , Constraint Manager , PCB design , test point , Allegro PCB Editor , OrCAD PCB Editor , Schematic , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—How to Verify SoCs Incorporating the M-PCIe Specification

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the…

• less than a min read
Whiteboard Wednesdays , IP , M-PCIe , mobile

Verification

Objection Mechanism Synchronization Between SystemVerilog and e Active Verification…

Suppose you have two verification components, each driving its own portion of the…

• 4 min read
AF , UVM-ML , e-SV , debug , objection mechanism , Functional Verification' signal integrity , Incisive Enterprise Simulator (IES)

Analog/Custom Design

Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online…

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose…

• 3 min read
EAD , AMS , Rapid Adoption Kit , ADE XL , Virtuoso Analog Design Environment , Monte Carlo , Layout , Virtuoso , Virtuosity , statistical corners , Virtuoso Layout Suite , IC 6.1.6

SoC and IP

IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

You know we live in astonishing times when you can start your car by talking into…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

System, PCB, & Package Design 

Create Ideal Solder Mask Openings Around Bond Fingers with Cadence 16.6 IC Packaging…

Exposing metal through solder mask openings is as necessary as it can be frustrating…

• 4 min read
IC Packaging and SiP Design , SiP , IC Packaging , SiP Design , IC package design , package design rules , Wirebond , SiP Layout , wire bond

System, PCB, & Package Design 

What's Good About Allegro Design Workbench Team Collaboration? Find Out in the 16…

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator…

• 1 min read
PCB , Cadence Design Systems , Allegro 16.6 , cadence , 16.6 , Allegro Design Workbench , Team design , SPB , design , PCB design , Grzenia , ADW

Whiteboard Wednesdays

Whiteboard Wednesdays - USB Controller Connectivity

In this week's Whiteboard Wednesdays, Jacek Duda continues his discussion about USB…

• less than a min read
Whiteboard Wednesdays , USB connectivity , HSIC , USB controllers , SSIC

Verification

Challenges and Applications in a 3D World

As the 3-D memory market matures, it continues to incubate new application opportunities…

• 1 min read
Verification IP , Memory , 2.5D Memory , 3D memory , VIP , Memory Model Portfolio , HMC , HBM , memory IP , Wide IO2 , MMAV

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Made Easy with Memory Models

In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their…

• less than a min read
Whiteboard Wednesdays , wide i/o , SoC , memory models , verifying memory interfaces

SoC and IP

Highlights from Recent IEEE 802.3 Ethernet Standards Meeting

I wanted to share with you a number of updates from last month's IEEE 802.3 meeting…

• 2 min read
25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet

System, PCB, & Package Design 

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

The signal integrity (SI) prophets had predicted this time would come, and it turns…

• 4 min read
Serial link analysis , DDR4 , BER Analysis , SystemSI , Power aware SI , Allegro Sigrity

Verification

Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the…

• 2 min read
SystemVerilog , uvm , profiling , Incisive , post-simulation profiling , verification

SoC and IP

IoT Focus: Natural User Interface Design Crucial to Success

Each era of electronics innovation is generally marked by a dominant end application…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Whiteboard Wednesdays

Whiteboard Wednesdays - How to Support Higher Performance Multimedia Applications…

In this week's Whiteboard Wednesdays, Charles Qi continues his discussion on hosted…

• less than a min read
Whiteboard Wednesdays , IP , hosted virtual desktop , user inputs processing , virtualized device enumeration , USB controllers , multimedia

System, PCB, & Package Design 

What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!

Just a brief post this week to mention a new capability for Allegro Design Entry…

• less than a min read
Allegro Design Entry , Allegro 16.6 , 16.6 , SPB , Design Entry HDL , PCB design , Design Entry

Verification

Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption…

The state-of-the-art Palladium XP hardware/software verification computing platform…

• 2 min read
ICE , sim accel , IXCOM , Palladium XP , COS Cadence Online Support , Simulation acceleration , hsv , RAKs , stb

Whiteboard Wednesdays

Whiteboard Wednesdays - The Evolution of NAND Flash

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need…

• less than a min read
Whiteboard Wednesdays , IP , BCH algorithm , NAND flash , error correction
CDNS - Fix Layout Hompage