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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

SoC and IP

AgigA Tech DDR3 memory module combines SDRAM and NAND Flash for data backup on one…

AgigA Tech, a memory-module vendor and a subsidiary of Cypress Semiconductor, has…

• 1 min read

Verification

I Think, Therefore I Blog (Cogito Ergo In Araneam Scribo)

I realized that I have just passed the second anniversary of my first blog post…

• 2 min read
uvm , CDNLive , blog

Verification

Ericsson Selects Specman Constrained-Random Verification To Improve Efficiency And…

Sarmad Dahir of Ericsson switched from directed testing to constrained-random test…

• less than a min read
Specman , VIP , Coverage-Driven Verification , EDA , Aspect Oriented Programming , MDV , AOP , IES-XL

System, PCB, & Package Design 

What's Good About DEHDL Anchor Point Wire Stretch? It's In SPB16.3!

Just a very quick post this week on a simple, but elegant new SPB16.3 feature for…

• 1 min read
PCB , SPB16.3 , Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Design Entry HDL , Front-end PCB design , PCB design , Design Entry , ConceptHDL

SoC and IP

The differential cost between SSDs and HDDs continue in today’s Fry’s ad. Giant flashing…

Today’s Fry’s Electronics ad on the back page of the first section of the San Jose…

• 3 min read

SoC and IP

Just what does “XXnm-class” mean for NAND Flash devices? Why the smoke? Why the mirrors…

Two days ago, I posted a short blog entry on Hynix’s new “20nm-class” 64Gbit NAND…

• 2 min read

Verification

e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages…

• 1 min read
IEEE 1647 , funtional verification , when sub-typing , TLM , Verification methodology , Object Oriented Programming , innovation , Functional Verification , Open Verification Methodology , when inheritance , Testbench simulation , OVM e , Coverage-Driven Verification , e , OVM-e , team specman , specman elite , OOP , coverage driven verification (CDV) , ClubT , Aspect Oriented Programming , esl tlm synthesis rtl dac estimation planning , macros , eRM , System Verification , Incisive Enterprise Simulator (IES) , hvl , IES , Coverage Driven Verification , Functional Verificatioa , OVMWorld , verification , IES-XL , Trailblazer

Digital Design

Abstracts For CDNLive! Silicon Valley 2010 Due August 22

Don't let the name CDNLive! confuse you. It's the Cadence user's group conference…

• 2 min read
Floorplanning , hierarchical design , Digital Implementation , CDNLive! , tcl

SoC and IP

Hynix initiates “20nm-class” NAND Flash production with 64Gbit devices

Hynix announced yesterday that it has begun mass production of 64Gbit NAND Flash…

• 1 min read

Digital Design

EDA Follow-The-Leader ... Signoff In The Design Flow

As a member of the EDA community, I find it interesting and somewhat frustrating…

• 1 min read

Verification

e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification…

• 2 min read
IEEE 1647 , funtional verification , IntelliGen , Specman , methodology , Object Oriented Programming , Functional Verification , Open Verification Methodology , specman job postings , OVM e , Incisive , jobs , e , OVM-e , team specman , specman elite , OOP , job postings , Aspect Oriented Programming , eRM , IEV , System Verification , Incisive Enterprise Simulator (IES) , hvl , AOP , IES-XL , Trailblazer

Verification

TLM-driven Design And Verification Methodology Book Author Interviews

The recently published TLM-driven Design and Verification Methodology book has been…

• less than a min read
TLM , methodology , Stellfox , Balarin , Mosenson , Bailey , Watanabe , McNamara , ESL , book

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL Test Setup

In my last post , I left you in suspense, with your mouse hovering over the words…

• 4 min read
IC 6.1 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Memcon 2010 proceedings now online

Last week’s MemCon 2010 was a blowout event, focusing on the past, present, and future…

• less than a min read

SoC and IP

The Woz Is Coming...The Woz Is Coming...The Woz Is Coming...and keynoting at the…

Just announced, Steve Wozniak will be speaking at the Flash Memory Summit this month…

• less than a min read

System, PCB, & Package Design 

What's Good About The PCB SI Model Editor? See For Yourself In The SPB16.3 Release

With the SPB16.3 release of PCB SI , the Model Editor has been added to allow you…

• 5 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , HSPICE , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB design , SI analysis and modeling , model editor , power

SoC and IP

Real comments on SSDs from the industry at large over at LinkedIn

It’s easy for pundits to flap their lips when speaking about SSDs. What’s harder…

• 4 min read

SoC and IP

I’ve been waiting for this: water-cooled DDR3 SDRAM from Kingston

Long, long ago in a galaxy far, far away--PC motherboards carried an array of chips…

• 2 min read

SoC and IP

Motley Fool investment site discovers SSDs, gets it wrong

The Motley Fool, a famous investment book turned Web site ( www.fool.com ) just posted…

• 2 min read
CDNS - Fix Layout Hompage