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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
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Blog - Post List

Latest blogs

Verification

SystemC Debug: A Summary of Summary Probes

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs…

• 5 min read
Verification planning and management , TLM , System Design and Verification , System simulation and analysis , debugging , ESL , verification

Analog/Custom Design

Don't Confuse Primary With Only

Given the small nature of the EDA industry, I have read with some interest company…

• 1 min read
mixed-signal simulators , CDNLive , Primary , analog , Sanyo , Cusstom IC Design

Verification

e Shareware on OVMWorld.org and Cadence Community Sites

As our loyal readers know, we on Team Specman works hard to include code examples…

• 1 min read
IEEE 1647 , Specman , Functional Verification , OVM e , vr_ad , e , team specman , OVMWorld , verification

System, PCB, & Package Design 

What's Good About New Smoke Analysis Devices? Check out the SPB16.2 Release and See

The AMS Simulator Smoke Analysis has been enhanced in the SPB16.2 release to support…

• 2 min read
SPB 16.2 , AMS simulator , Smoke Analysis , PCB design , model editor

Verification

ISX Presentations at CDNLive! Munich

As we head into next weeks CDNLive! event in Munich it's great to see today's post…

• 1 min read
cdnlive! emea 2009 , System Design and Verification , ISX

SoC and IP

Taiwan: From Death by DRAMs to Finding Foundry Success

Vanguard International Semiconductor, Once a DRAM failure, is Now a Successful Junior…

• 7 min read

SoC and IP

Taiwan DRAM Makers...Trapped by Their Culture?

Can Taiwanese DRAM Makers Decide What to do Next...in Time? We recently saw…

• 3 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Introduction

A while ago, I somehow ended up on the mailing list of a rather odd catalog called…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

IEEE P1647-2010 Call For Participation

Attention Specmaniacs: the IEEE 1647 working group is looking for a few additional…

• 2 min read
IEEE 1647 , Specman , Functional Verification' signal integrity , OVM e , e , OVM-e , eRM , AOP

Verification

CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 18-20 is the annual…

• 3 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

SoC and IP

Cross Currents in Memory Market Signal Changes Ahead

No one can say with any certainty, but... Recent improvements in DRAM and NAND…

• 6 min read

Verification

Modeling Interfaces with C-to-Silicon Compiler

Users of ESL tools are curious about the procedure for handling the interface to…

• 2 min read
CTOS , System Design and Verification , TLM 2.0 , SystemC analysis , C-to-Silicon , transaction level modeling , high level synthesis , Modeling , HLS , dma

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 3

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM…

• 7 min read
TLM , simvision , System Design & Verification , ESL

Verification

e Coding Made Easy with the “DVT” Integrated Development Environment

Specmaniacs everywhere should be aware of a great, full-featured integrated development…

• 6 min read
IEEE 1647 , SystemVerilog , eclipse , Specman , CDNLive , Functional Verification , OVM , OVM e , OVM SV , e , specman elite , AMIQ , eRM

Verification

It's Not Too Early to Think About DAC 2009

Even though it's still a couple of months off, it's not too early to think about…

• 1 min read
DAC 2009 , System Design and Verification , hardware-dependent software

Verification

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Analog/Custom Design

Jurassic Park IV: The Return of ANALOG

In the lab, no one can hear you scream! When I was getting my BSEE in the…

• 2 min read
analog , Incisive , encounter , Virtuoso , RF design , Custom IC Design

Digital Design

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Digital Design

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1
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