Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

What's Good About HDI Via Structures - Check out the SPB16.2 Release and See!

New functionality has been added to the SPB16.2 Allegro PCB Editor suite of tools…

• 12 min read
SPB 16.2 , LMB , via , PCB design , microvia

Digital Design

Coming This Friday November 14th: SoC-Encounter Office Hours

I've really been enjoying the discussions in our Digital Implementation Forums…

• 1 min read
SoC-Encounter , Digital Implementation forums , chat

Digital Design

How to Change a Net Name

This is a question that comes up once every few months or so: "How do I change the…

• less than a min read
Digital Implementation

Digital Design

Demo: Partitioning a Design in SoC-Encounter

One of the longest standing capabilities in SoC-Encounter is its ability to partition…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , screencast , Digital Implementation

Verification

Heads-up: Formal + Productivity Flow Technical Webinar Coming Up On Nov 12th

Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper…

• 2 min read
FPV , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV)

System, PCB, & Package Design 

What's Good About The SPB16.2 Release? WOW - Download It now!

The SPB16.2 release is now available (actually, it was available on 10/31/08 from…

• 2 min read
SPB 16.2 , PCB design , Allegro

Verification

Portable Design Names Cadence Incisive Palladium Dynamic Power Analysis its September…

In his article in Portable Design, John Donovan wrote: Palladium Dynamic Power Analysis…

• less than a min read
Portable Design , System Design and Verification , Palladium

Verification

Welcome Sharath Siddappa From Rambus, You Are The 5000th OVM World Registrant!

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the…

• 1 min read
SystemVerilog , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , eRM , OVMWorld

Verification

OVM - The "O" Means Opportunity

A few months back I blogged that OVM was " Open for Business ". A nice play on words…

• 1 min read
Simantis , eclipse , KPIT , Functional Verification , IBM , Cadence VIP portfolio , OVM , Doulos

Verification

Report From the Advanced Verification Techtorial in San Jose Tuesday 10/28

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Verification

The Power of Cadence System Power Flow vs. Viewing from the Top

I feel that I must respond to the following blog published by Frank Schirrmeister…

• 6 min read
Incyte Chip , System Design and Verification , Incisive Enterprise Simulator , Palladium , power engineer , C-to-Silicon , Power Analysis , Frank Schirrmeister

Verification

ESC Boston: Day 2

This morning before heading to ESC it dawned on me that the park across the street…

• 4 min read
System Design and Verification , ESC , ISX , Coverage Driven Verification

Analog/Custom Design

Video Demo: ViVA-XL - Fast Waveform Viewing

It’s happened to each of us at some point in time. Your long simulation is finally…

• less than a min read
ViVa-XL , MMSIM , Simulators , Custom IC Design , Fast Waveform Viewing

System, PCB, & Package Design 

What's Good About Directive Locking?

Do you wish you could lock specific aspects of a DEHDL design content? Do you need…

• 5 min read
CPM Directive Control , DEHDL , Directive Lockhing , PCB design , SPB16.01

Verification

Virtualization Taxonomy

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's…

• 2 min read
VM ware , virtualization , taxonomy , real-time systems , Embedded Systems Conference , System Design and Verification , ESC

Verification

OVM Momentum and Interoperability

The question of how to integrate legacy VMM VIP into OVM verification environments…

• 1 min read
OVM Professionals Network , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , VIP , Verification IP modeling

Verification

Verification Techtorial in San Jose next Tuesday 10/28

Apologies for the shameless promotion, but I can't resist touting an event I'm producing…

• less than a min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Verification

Formal Moment Of Zen

Most of my experience in functional verification prior to my dabbling in FPV was…

• 3 min read
OVL , FPV , Functional Verification , Formal Analysis , SCV , SVA , FIFO , PSL , Simulation acceleration , SystemC

System, PCB, & Package Design 

Need some stability in your Package Power?

It is not too late to sign up for the Package Power Integrity webinar that will be…

• less than a min read
PDN , IC Packaging & SiP design , SPB16.2 , SSN
CDNS - Fix Layout Hompage