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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Breakfast Bytes

DVCon 2022 Preview

DVCon 2022 is coming up soon from February 28th to March 3rd. It is entirely virtual…

• 7 min read
dvcon 2022 , uvm , pss , fusa , verification

Computational Fluid Dynamics

The World’s Energy Diet Shifts into Electrification

In the last two years, businesses worldwide faced several challenges and have had…

• 3 min read
Automotive , Tesla Cybertruck , Electrification , Audi , electric vehicles , autonomous driving , Audi etron , Electric Car Rental , tesla , Lithium-Ion Batteries , battery , Energy storage

Verification

SoCs Verification Management, Traceability and Managing Risks in Semiconductor W…

With the increased complexity in SoC design and bigger teams, manually updating the…

• 4 min read
Verification planning and management , collaboration , vPlan , IBM , verification management , JIRA , Traceability , OpsHub , IBM DOORS NG , semiconductors , vManager

System, PCB, & Package Design 

(P)SpiceItUp: Sweeping Multiple Parameters to Enhance Performance

Often you want to see the effect of changing multiple parameters on the performance…

• 7 min read
17.4 , PSpiceA/D , (P)SpiceItUp , 17.4-2019 , OrCAD , PSpice Advanced Analysis , simulation

The India Circuit

Join Cadence at VLSID 2022 Next Week!

VLSID 2022, the 35th International Conference of VLSI Design and the 21st International…

• 2 min read
VLSID 2022 , VLSI & Embedded Systems Design Conference

Breakfast Bytes

Sunday Brunch Video for 20th February 2022

https://youtu.be/jGAKLppD9YE Made in Lumen5 by me Monday: Generic and Open PDKs…

• less than a min read
sunday brunch

Academic Network

Opening a Certified EDA lab at Sofia University in Bulgaria

A few months ago, I was contacted by Dobromir Gaydazhiev, director of Design Support…

• 2 min read
Cadence Academic Network , Certified Lab , Sofia University , gf

Breakfast Bytes

Offtopic: Sudoku and Wordle

Tomorrow is a Cadence "global recharge day" and Monday is Presidents' Day in the…

• 6 min read
offtopic , wordle , Sudoku

Computational Fluid Dynamics

What Battery Energy Density is Required for Long-Distance Electric Aircraft?

Birds inspired us to develop aircrafts capable of flight. Before the Wright brothers…

• 2 min read
Lithium Air Batteries , electric planes , greenhouse gases , Computational Fluid Dynamics , batteries , Sodium-Sulfur Batteries , Lithium Ion Batteries , engineering

Digital Design

Adopting a Faster, More Efficient Path to Multi-Chiplet Design

Gone are the days when process shrinking was considered as the primary driver of…

• 3 min read
chiplets , 3D-IC , Integrity , Thermal Integrity , system planning , Multi-Chiplet Design

Breakfast Bytes

Automotive: CFD, FuSa, Aging, Vision, Light

That's a lot of acronyms and buzzwords! Just in case you don't know them all, they…

• 5 min read
CFD , Automotive , functional safety , Tensilica , vision , aging

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Configuring OrCAD and Allegro Installations…

Often, you install the Cadence products with default settings and that suffices to…

• 4 min read
Installation Know-How , 17.4 , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , OrCAD , installation , Allegro

Breakfast Bytes

China, US, Europe: Everybody's Got a CHIPS Act

I ran across a very interesting report from the Semiconductor Industry Association…

• 5 min read
asml , China , SIA , US CHIPS Act , Europe Chips Act

Breakfast Bytes

Generic and Open PDKs

One challenge that educators and researchers face is that they typically have no…

• 4 min read
Open PDK , openroad , google , PDK , efabless

Computational Fluid Dynamics

Simulate Wind Turbine Blade Aerodynamics Using High-Quality Automated Meshing

Dr. Galih Bangga, a scientist with a forte in wind energy research, from the Institute…

• 3 min read
CFD , Meshing Monday , Mesh metrics , Automated meshing , engineering , simulation software , Cadence Pointwise , Mesh Generation , Meshing

Breakfast Bytes

Sunday Brunch Video for 13th February 2022

https://youtu.be/_Rt6kAURffU Made in Rancho San Antonio County Park (camera Carey…

• less than a min read
sunday brunch

Breakfast Bytes

January Update

I realize that it is February, but I was sick late January and so I never wrote this…

• 5 min read
Intel , risc-v , NVIDIA , update , ARM , agriculture

Learning and Support

Webinar Invitation: Enhance your Design Power with Joules

Want to take a tour of this powerful power estimation tool and gear up so you understand…

• 2 min read
Cadence Support Portal , Cadence support , cadence learning and support

Breakfast Bytes

CadenceLIVE Silicon Valley 2022: You Can Be Part of the Event

CadenceLIVE Silicon Valley is scheduled for June 8 and 9, and currently it is planned…

• 1 min read
cadencelive
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