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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Verification

And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly…

• 1 min read
DVCon 2019 , paper , Functional Verification , award

Breakfast Bytes

PSA: Americans Will Need Visas for Europe

From 2021, Americans will need a visa for Europe. You read it here first! That means…

• 6 min read
visa , Europe , schengen

Analog/Custom Design

Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with…

• 2 min read
VCD , Analog Design Environment , ICADVM18.1 , analog , ViVA , Virtuosity , analog stimuli , IC6.1.8 , vector

Breakfast Bytes

Gin and Tonic: The Drink of Barcelona

One thing that is a big deal in Barcelona is gin and tonic, or G&T as it is usually…

• 6 min read
barcelona , MWC

Breakfast Bytes

CDNLive: Travels with a Bear

It's nearly time for the season of CDNLive events, which starts as always in Silicon…

• 5 min read
CDNLive

Analog/Custom Design

Virtuosity: Identifying Those Traces

With the ever-increasing number of simulations required to be run these days, the…

• 3 min read
Explorer , plotting , ADE XL , Virtuoso , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Assembler

Whiteboard Wednesdays

Whiteboard Wednesdays - Diagnostics – What Makes Modus Diagnostics an Industry Leading…

Cadence distinguished engineer Rohit Kapur introduces diagnostic capabilities in…

• less than a min read
Whiteboard Wednesdays , modus

Breakfast Bytes

MWC Part Dos

Yesterday I wrote my first post about MWC19 Barcelona . Today is the continuation…

• 8 min read
5G , MWC , daimler , BMW , ARM

Breakfast Bytes

MWC Barcelona

Last week it was MWC Barcelona. As seems to be the fashion, like with CES, MWC just…

• 7 min read
5G , gsma , MWC , mobile , vodaphone

Breakfast Bytes

Sunday Brunch Video for 4th March 2019

https://youtu.be/wjX4hOvb9-I Made at MWC19 Barcelona (camera JD Estella) Monday…

• less than a min read
Automotive , connx b20 , lidar , mwc19 , radar , MWC , 112g , v2x , SerDes , mobile , bitcoin , Sigrity , ARM , Breakfast Bytes , blockchain

PCB、IC封装：设计与仿真分析

Allegro PCB Editor: 进阶使用技巧

本文将和大家分享Allegro PCB Editor的进阶使用技巧，旨在利用快捷键操作而减少鼠标点击次数，同时包含了定制特定的应用环境，让工具发挥最大效率的方法和示例…

• less than a min read
Chinese blog , 软件技巧 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro

Breakfast Bytes

Who Is Satoshi Nakamoto?

Nobody knows. Really. Here's what is known. He (or maybe it's she or they) is the…

• 8 min read
satoshi nakamoto , cyptography , bitcoin , blockchain

Life at Cadence

International Women's Day

Cadence hosts Girls Who Code founder and CEO Reshma Saujani for talk Cadence is…

FormerMember • 1 min read
Insights on Culture , STEM , Women's Day , Reshma Saujani , International Women's Day

Breakfast Bytes

Signal Integrity for 112G

At DesignCon at the end of January, a team from Cadence presented to a standing-room…

• 5 min read
AMI , pam4 , 112Gbps , 112g , SerDes , Sigrity , SystemSI

Analog/Custom Design

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out

While most of us would like our electronic gadgets to last forever, the reality is…

• 3 min read
Stress Analysis , TDDB , PBTI , native reliability analysis , Spectre , reliability analysis , HCI , NBTI , reliability

Breakfast Bytes

DesignCon: 5G for V2X Communication

One of the keynotes at the recent DesignCon was by Robert Heath of UT Austin titled…

• 5 min read
5G , Automotive , DesignCon

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the ConnX Family with B10 and B20

In this week’s Whiteboard Wednesdays, Pierre-Xavier Thomas introduces the B10 and…

• less than a min read
Whiteboard Wednesdays , ConnX

Analog/Custom Design

Virtuosity: New Flexible Subwindows

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or…

• 3 min read
ICADVM18.1 , subwindows , waveforms , Virtuoso Analog Design Environment , ViVA , Virtuosity , plotting templates , Custom IC Design , IC6.1.8

Breakfast Bytes

Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar

I'm sure you've noticed that there is a lot of talk about 5G in the air. Well, "in…

• 6 min read
5G , connx b20 , lidar , radar , Tensilica
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