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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 3 of 4)

In part 2 of this blog series we looked at the three different modes of heat transfer…

• 8 min read
EE Thermal , temperature , Thermal Basics , Heat transfer , PowerDC

Breakfast Bytes

CHIPs in the Cadence Cafeteria

Last week it was the Annual San Jose Intern Showcase, in which the San Jose based…

• 4 min read
Interns , intern showcase , chips

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由

Cadence Allegro 17.2-2016是过去十年中发布的最大版本，于2016年4月下旬发布。由于17.2-2016版本包含数据库更改，通常会出现在零版本中…

• 1 min read
PCB , Chinese blog , Allegro 17.2 , 升级 , Allegro GUI , 约束管理器 , 布线 , 约束驱动的PCB设计流程 , PCB设计 , 中文 , OrCAD , Sigrity , Allegro PCB Editor , 刚柔结合 , Allegro

Breakfast Bytes

CDNLive Japan: The Fourth Industrial Revolution and the Third Dimension

At CDNLive Japan, Tom Beckley gave the keynote Enabling the Fourth Industrial Revolution…

• 8 min read
cdnlive japan , Tom Beckley , Power Integrity , 4th industrial revolution , Signal Integrity , Thermal Analysis , Sigrity

Analog/Custom Design

Virtuoso: The Next Overture – DRD Launches New Interface

If you’ve been anywhere near the Cadence news buzz the last couple of months, you…

• 3 min read
Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , DRD , New in EDA , Custom IC Design , Custom IC

Breakfast Bytes

Lung Chu on Semiconductor in China

I talked Friday about the Chinese American Semiconductor Professionals Association…

• 5 min read
China , semicon , semi

The India Circuit

Of HD Maps, Road Safety And Deep Networks

Cadence India hosted a first-of-its-kind seminar recently that talked about the need…

• 3 min read
artificial intelligence , deep learning , IISC , Netradyne , Indian Institute of Science , Cadence India , AI

PCB、IC封装：设计与仿真分析

警惕发热！——热模型交换

如今，工程师们面临着复杂且快速的设计变更，需要运用多个设计工具才能协同完成。 MCAD和ECAD的设计系统由于采用其中性文件格式（如SAT、IGES、IDF等）…

• less than a min read
CFD , 热 , PI , Chinese blog , 电源完整性 , 仿真分析 , 电热协同仿真 , Power Integrity , 中文 , Sigrity , 中性文件格式 , PowerDC

Breakfast Bytes

Simulation in the Cloud

Yes, despite the blue skies, Fridays are still cloudy. And, yes, this isn't Friday…

• 5 min read
rocketick , cadence cloud , xcelium , simulation

PCB、IC封装：设计与仿真分析

封装/ PCB系统的热分析：挑战及对策

如今越来越多的封装/ PCB系统设计需要进行热分析。 功耗是封装/ PCB系统设计中的关键问题，需要仔细考虑热和电两个领域的问题。 为了更好地理解热分析，我们以固体中的热传导为例…

• 2 min read
PCB , 热 , PI , Chinese blog , 电源完整性 , 电热协同仿真 , Power Integrity , Voltus , 中文 , Sigrity , PowerDC

PCB、IC封装：设计与仿真分析

欢迎访问Cadence公司PCB、IC封装：设计与仿真分析博客

我们将与您分享有关PCB和IC封装设计与仿真分析的最新资讯； 在这里，您可以纵观科技前沿、行业动态与展会讯息； 在这里，您可以获得如下专题的详细信息： • 最新产品…

• less than a min read
PCB , Chinese blog , 仿真分析 , 博客 , IC封装设计 , PCB与IC封装仿真分析 , PCB设计 , 中文 , Sigrity , Allegro

Breakfast Bytes

CASPA: Innovation with Chinese Characteristics

A couple of times per year, the Chinese American Semiconductor Professionals Association…

• 9 min read
risc-v , China , lithium battery , semi , lithium ion , caspa , sitri , battery , sifive

Breakfast Bytes

What's For Breakfast? Video Preview August 7th to 11th 2018

https://youtu.be/xPVzOfBHGlM Coming from Cadence Intern Showcase (camera Sean…

• less than a min read

Digital Design

QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

Whenever we talk to potential customers about Stratus HLS , we usually mention that…

• 4 min read
High-Level Synthesis , Stratus , SystemC , HLS

Analog/Custom Design

Virtuoso Video Diary: Single Schematic Flow in Virtuoso System Design Platform

The Single Schematic Flow in Virtuoso System Design Platform simplifies the product…

• 2 min read
vsdp , Virtuoso , Schematic Editor , Virtuoso Video Diary , Custom IC Design , single schematic , Schematic

Breakfast Bytes

ITF: CFETs and New Interconnect

At the imec technology forum (ITF) held the day before SEMICON West opened, two of…

• 8 min read
3nm , cfet , ruthenium , imec , itf

Breakfast Bytes

How to Pitch a Journalist

In the early part of my career, I was an engineer or an engineering manager. Then…

• 7 min read
journalism , marketing

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the…

• less than a min read
Whiteboard Wednesdays , ccix , cloud

Verification

Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meet…

We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it…

• 2 min read
Functional Verification , DAC 2018 , Altia Systems , xcelium
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