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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Four Uses for the Venerable Virtual Platform UART

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware…

• 2 min read

System, PCB, & Package Design 

What's Good About APD’s Assembly DRCs? You’ll Need the 16.5 Release to See!

Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC…

• 25 min read
PCB , PCB Layout and routing , IC Packaging , DRC , APD , ADRC , Allegro 16.5 , SPB , PCB Editor , advanced package designer , Layout , assembly DRCs , "PCB design" , PCB design , SPB16.5 , Allegro

Verification

ARM Generic Interrupt Controller HOWTO

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software…

• 5 min read
Virtual System Platform , Cortex-A9 , System Design and Verification , Cortex-A , howto , ARM Generic Interrupt Controller , SystemC , GIC , ARM , Wadikar , Generic Interrupt Controller

Verification

Some Reflections on the Development of UVM World

In a recent blog post , I celebrated our donation of the Cadence-developed UVM…

• 3 min read
uvmworld.org , uvm , uvm world , Functional Verification , OVM , universal verification methodology , Accellera , verification

Verification

Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my…

• 1 min read
Brian Fuller , DAC , Joe Hupcey III , tweeting , videos , interview , Blogging , YouTube , blogs , Facebook , OrCAD , CtoSilicon , Twitter , Social Media , EE Times , DAC360

Verification

Enterprise Planner - CSV Import Tech Tip

Are you interested in an automating your directed or random test list that you manually…

• 1 min read
metric-driven , Functional Verification , Metric Driven Verification , CSV , vPlan , tech tips , EDA360 , Incisive , Enterprise Manager , Enterprise Planner , MDV , Excel , verification

Verification

Creating SystemC TLM-2.0 Peripheral Models

Over two years ago, I made some experiments and raised some requirements for an effective…

• 8 min read
Virtual System Platform , virtual platforms , TLM , IP-XACT , Models , virtual prototypes , System Design and Verification , TLM 2.0 , embedded software , VSP , TLM-2.0 , Team ESL , peripheral , SystemC , ESL

Digital Design

Five-Minute Tutorial: Finding EDI Videos

I've seen a few requests in the forums asking about EDI videos. Today I will show…

• less than a min read
COS , EDI , video , encounter , Digital Implementation , five minute tutorial , 5 minute tutorial

System, PCB, & Package Design 

What's Good About Allegro GRE Route Around Etch Shapes? See For Yourself in 16.5

This new 16.5 Global Route Environment ( GRE ) functionality was designed to allow…

• 1 min read
PCB , PCB Layout and routing , global route , Routing , Allegro 16.5 , SPB , PCB Editor , Layout , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , GRE , etch shapes

Verification

More Examples of Missing Real-World Assertions

Back in May, I published a blog post with examples of real-world situations that…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

Analog/Custom Design

Things You Didn't Know About Virtuoso: Viva ViVA!

I realize that I have been quite remiss in that I have not yet blogged about the…

• 1 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , Analog Simulation , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , ViVA , ADE-XL , Custom IC Design

Verification

Celebrating the Success of the UVM World Web Site

In case you missed it, Cadence issued a press release last week announcing that we…

• 2 min read
uvm , uvm world , universal verification methodology , Accellera

Analog/Custom Design

Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

The creation of behavioral models is only one part of the process of using those…

• 3 min read
AMS , Virtuoso-AMS , mixed signal design , AMS-Designer , amsDMVAMS-Designer , Verilog-AMS , analog , Mixed-Signal , model validation , mixed signal , wreal

Verification

True Stories of Assertion Driven Simulation (ADS) in the Wild

Ever since Assertion-Driven Simulation (ADS) became available, I have been working…

• 4 min read
AXI , ABV , Verification methodology , Functional Verification , Formal Analysis , ABVIP , formal , simvision , VIP , ADS , DDR , Club Formal , Constraints , IEV , Assertion-Driven Simulation , Formal verification , Assertion-based verification

SoC and IP

Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design…

• less than a min read
controller IP , Design IP , PCI Express 3.0 , Gen3 , PIPE , PCI , PCI-SIG

Verification

Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System…

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers…

• less than a min read
DAC , uvm , debug , system realization , Mike Stellfox , Accellera , SystemC , Trailblazer

System, PCB, & Package Design 

What's Good About Allegro PCB Router Region Rules? 16.5 has a few new enhancements

Designers normally create nets or groups of nets to assign constraints. This leads…

• 1 min read
PCB , PCB Layout and routing , Constraint-driven PCB Design flow , global route , Routing , Allegro 16.5 , PCB Editor , Layout , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Before DAC, There Was Club Formal – An Event Series Completely Focused on Formal…

To complement our support of DAC, CDNLive, and other large-scale events, where the…

• 1 min read
events , ABV , verification strategy , Functional Verification , Formal Analysis , formal , Incisive , Incisive Seminar , ADS , Oski Technology , Silicon Realization , assertions , Club Formal , ClubT , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Verification

Full Sequence Coverage in a Single Line of e Code?

I was asked recently about how to easily collect coverage on the sequences generated…

• 1 min read
Specman , e , OVM-e , e language , team specman , specman elite , AOP
CDNS - Fix Layout Hompage