Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through…

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high…

• 1 min read

Verification

A Quick Check on the Status of UVM 1.0

Regular readers know that I've blogged a lot about the Open Verification Methodology…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

SoC and IP

LSI Corp to host IC innovation conference and technology showcase in Milpitas next…

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase…

• 1 min read

Verification

Will Your Next System Project Succeed?

Will you have the System Realization tools you need? Will you know how to apply them…

• 3 min read
TLM , webinars , system realization , TSMC , services , ARM , ESL , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI DML Path Setting? See For Yourself in the SPB16.3 Release

With the SPB16.3 release of Allegro PCB SI , there’s a new methodology for Device…

• 4 min read
PCB SI , PCB , SI , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB Editor , design , PCB design , SI analysis and modeling , dml

Digital Design

Guest Blog: Using dbTransform to Translate Geometric Coordinates in Encounter

This is a guest post from JasonG at Avago. I hope you enjoy this useful piece he…

• 4 min read
Avago , dbTransform , encounter , db access , Digital Implementation , tcl

SoC and IP

New Blog: EDA360 Insider, for anyone involved with any aspect of system design

I’ve just started a new blog called the EDA360 Insider ( http://eda360insider.wordpress…

• less than a min read

SoC and IP

Samsung rolls 8Gbyte DDR3 SODIMM, Dell picks it up immediately, stuffs four into…

Samsung has announced that it is now shipping 8Gbyte DDR3 SODIMM SDRAM modules for…

• less than a min read

Verification

Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With…

Lately the tone of the trade press and blogs about the Silicon Valley electronics…

• less than a min read
uvm , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Chu , verification

Analog/Custom Design

Now Playing: Custom IC Videos-to-Go

I wanted to take a brief detour from my usual postings to point out a couple of new…

• 3 min read
IC 6.1 , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

DRAMeXchange ranks NAND Flash vendors for Q210. Samsung wins, again.

Last month, DRAMeXchange published rankings for the top “branded” NAND Flash vendors…

• 1 min read

Digital Design

Encounter Puzzler #2 Solution: Finding Registers Beneath a Hierarchy

Thanks to everyone who participated in this week's Encounter Puzzer . If you didn…

• 6 min read
dbGet , encounter , Digital Implementation , puzzler , tcl

SoC and IP

JEDEC launches new SSD reliability standards, plans in-depth SSD tutorial in San…

An article in ComputerWorld reports that JEDEC (www.jedec.org) has just announced…

• less than a min read

SoC and IP

Crucial SSDs hit $1/Gbyte, with a crucial caveat

The Bright Side of News (BSN, www.bsn.com) Web site reports today that Crucial is…

• less than a min read

Digital Design

Five-Minute Tutorial: Creating a NONDEFAULT Rule

Ah, the NONDEFAULT rule. This is a routing rule that is, well, not the default! It…

• 2 min read
nondefault rule , EDI system , tutorial , encounter , Digital Implementation , nondefault , five minute , five-minute

SoC and IP

Top 10 SSD benefits: Samsung publishes list

Samsung, SSD vendor and the world’s leader in Flash memory, has just published a…

• 1 min read

SoC and IP

Oracle optimizes Unbreakable Linux for SSDs. Improves access times by 137%.

This week at its OpenWorld event held in San Francisco, Oracle announced the Unbreakable…

• 1 min read

System, PCB, & Package Design 

What's Good About Differential Impedance in Allegro Constraint Manager? It's in SPB16

The ability to constrain or report Differential Impedance from within Constraint…

• 2 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , DRC , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , design , PCB design , Allegro PCB Editor , SI analysis and modeling , Differential Pair Support , power

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL -- Where Did My Data Go?

Last week I got to attend a "Social Media Summit" here at Cadence. Jeepers, a "summit…

• 3 min read
Analog Simulation , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design
CDNS - Fix Layout Hompage