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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays – xSPI Standard Explained

In this week’s Whiteboard Wednesdays video, Jacek Duda explains the xSPI standard…

• less than a min read
Whiteboard Wednesdays , xSPI , JEDEC

Analog/Custom Design

Virtuoso IC6.1.8 ISR5 and ICADVM18.1 ISR5 Now Available

The IC6.1.8 ISR5 and ICADVM18.1 ISR5 production releases are now available for download…

• 2 min read
ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , Automated Device-Level Placement and Routing , Automatic Placement , Interactive and Assisted Routing , Virtuoso RF , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8 , ADE Assembler

Analog/Custom Design

Spectre Tech Tips: Spectre Local Options

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use…

• 7 min read
highvoltage , spectre aps , scale , skip , Spectre , reltol , scoped options , vrefgnd

Breakfast Bytes

5G in US vs Rest-of-World

While I was in Germany for the Automobil Elektronik Kongress, the results of the…

• 7 min read
5G , mmwave , mobile

定制IC芯片设计

Virtuoso视频日记: 比较多个测试和共享设置

今天的博客重点介绍了现在ADE Assembler中提供的新Multi-Test Editor的功能。通过这个博客，我们已经结束了迷你博客系列，其中涵盖了 Virtuoso…

• 1 min read
Chinese blog , Analog Design Environment , ICADVM18.1 , ADE , simulator options , Virtuoso Video Diary , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Verification

Tales from DAC: Altair's HERO Is Your Hero

Emulators are great. They vastly speed up verification to the point where it’s hard…

• 2 min read
Cadence Theater , HERO , Palladium , Altair Engineering , DAC 2019

Breakfast Bytes

Ludwigsburg: It's All About Return-on-Investment

I attended the Automobil Elektronik Kongress at Ludwigsburg outside Stuttgart. it…

• 6 min read
Automotive , Automotiv Elektronik Kongress , ludwigsburg , ADAS

Breakfast Bytes

Sunday Brunch Video for 28th July 2019

https://youtu.be/-36euXtgU7Y Made at Cadence Summer of Love Party (camera Chad Yee…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

开放注册：2019 Cadence中国用户大会

Cadence中国用户大会 CDNLive China 2019 上海浦东嘉里大酒店 - 2019年8月15日星期四 space 亲爱的用户朋友： 一年一度的Cadence全球用户大会CDNLive…

• less than a min read
PCB , Chinese blog , CDNLive , CDNLive 2019 , 中文 , cdnlive china , Sigrity , 中国用户大会 , Allegro

System, PCB, & Package Design 

BoardSurfers: Designing a Rigid-Flex Board Using PCB Editor

Whether you are designing the latest pace-maker or a LED strip, you have definitely…

• 4 min read
PCB Editor , Rigid-Flex

Breakfast Bytes

Digital Twins at the Paris Air Show

The idea of a digital twin should be easy for anyone in aerospace to understand.…

• 5 min read
Aerospace , Protium , Palladium , digital twin , paris air show , verification

Breakfast Bytes

Galileo Down for a Week

You might never have heard of Galileo, the European Union's GNSS, or Global Navigation…

• 4 min read
Galileo , GPS , mobile

Computational Fluid Dynamics

Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpr…

Authors: Akio Takamura, Chief Engineer, Honda R&D, and Benoit Mallol, Head of Marine…

• 3 min read
CFD , Automotive , Computational Fluid Dynamics , fluid dynamics , Meshing , simulation

定制IC芯片设计

Virtuoso 视频日记: 下一件大事 - ADE Verifier与Cadence vManager合作

今天的博客重点介绍了ADE Verifier的最新增强功能。这个博客我们每周二和周四发布的迷你博客系列的一部分，以涵盖 Virtuoso®ADE Assembler…

• 1 min read
verifier , Chinese blog , ICADVM18.1 , Functional Verification , Formalized Verification , vPlan , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso Video Diary , ADE Blog Series , mixed signal , mixed-signal design , Custom IC Design , Custom IC , ADE Verifier , IC6.1.8 , vManager , verification

Verification

Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Thin…

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but…

• 2 min read
DAC 2019 , Semiconductor , cadence cloud

Analog/Custom Design

Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

Really, can Virtuoso bind strict? And what does that mean? Read along to find out…

• 2 min read
Update Binding , ICADVM18.1 , Layout XL Environment Variables , cdsenv , Virtuoso , Check Against Source , bindStrict , Custom IC Design , Update Components And Nets , Binder , IC6.1.8 , Virtuoso Layout Suite XL , binding

Breakfast Bytes

Computer Scientist Alan Turing to Be on British £50 Note

Last week the Bank of England announced that the new £50 note will have Alan Turing…

• 7 min read
bletchley park , turing award , alan turing

Whiteboard Wednesdays

Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols…

• less than a min read
Whiteboard Wednesdays , PHY IP , ONFI 4.x

Breakfast Bytes

Virtuoso Meets Maxwell

When I was a postgraduate at Edinburgh University, my office was in the James Clerk…

• 3 min read
RF , maxwell , Virtuoso
CDNS - Fix Layout Hompage