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Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

How Technologies Get into EDA

When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different…

• 6 min read
sales , startups , ambit , Signal Integrity , salesforce

Breakfast Bytes

Persistent Memory at Twitter

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent…

• 3 min read
persistent memory summit , Oracle , optane , Twitter , persistent memory

Verification

USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic…

• 1 min read
Verification IP , DP , DisplayPort , USB , usb4 , PCIe , tunneling

Breakfast Bytes

Persistent Memory: We Have Cleared the Tower

Last week it was the Persistent Memory Summit 2020, which has been running annually…

• 7 min read
persistent memory summit , persistent memory , 3dxpoint

Breakfast Bytes

Quarry Bank Mill: A Technology Museum from the Industrial Revolution

A couple of years ago (and from time to time since) I wrote a series of blog posts…

• 5 min read
industrial revolution , museum

Breakfast Bytes

Sigrity Aurora: In-Design Analysis

Cadence's new Sigrity Aurora puts all the power of the Sigrity engines under the…

• 3 min read
Sigrity Aurora , Signal Integrity , Sigrity

Life at Cadence

Intelligent System Design

Electronics technology is proliferating to new, creative applications and appearing…

• 9 min read
intelligent system design

System, PCB, & Package Design 

IC Packagers: Mysteries Revealed - Why Is Flip-Chip Chip-Down the Default Library…

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper…

• 4 min read
Allegro Package Designer

Breakfast Bytes

IEDM: Novel Interconnect Techniques Beyond 3nm

During the short course on the Sunday before IEDM, Chris Wilson of imec presented…

• 4 min read
interconnect , imec , IEDM

Breakfast Bytes

RIP Clayton Christensen

Clayton Christensen died last Thursday, at the relatively young age of 67. He was…

• 6 min read
clayton christensen , innovator's dilemma

Analog/Custom Design

Virtuosity: Reminiscing About The Last 'Teen' Year of Custom IC Design Blogs

If you have missed reading any of our Virtuosity, Virtuoso Meets Maxwell, Virtuoso…

• 3 min read
ICADVM18.1 , Automated Device-Level Placement and Routing , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Virtuosity , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

IEDM: TSMC on 3nm Device Options

At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and…

• 4 min read
TSMC , IEDM

System, PCB, & Package Design 

BoardSurfers: Leveraging IPC-2581 Spec Element Capabilities to Streamline Design…

If you are a PCB designer and follow IPC-2581 guidelines to design a board, this…

• 3 min read
Manuafacturing , PCB Editor , 17.4-2019 , IPC-2581

Breakfast Bytes

DesignCon 2020: SI, PCB, Packaging, Photonics

Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the…

• 3 min read
PCB , DesignCon , Signal Integrity , OrCAD , Sigrity , Allegro

System, PCB, & Package Design 

DATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process Contr…

Do you dread your ECAD to PLM publishing process? If yes, worry not. We have a solution…

• 1 min read
System Capture , allegro edm , PCB design , Pulse , PLM

Breakfast Bytes

IEDM: Automating DTCO for 3nm

At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization…

• 4 min read
3nm , IEDM , DTCO

定制IC芯片设计

Virtuosity：Modgen中的布局重用流程

Modgen 现在支持布局重用流. 请继续阅读，了解如何使用此功能通过减少创建 Modgen 的时间和精力来提高版图效率.

• less than a min read
Chinese blog , Modgen On Canvas , ICADVM18.1 , MODGEN , Layout Suite , Layout , Virtuoso , Virtuosity , Layout design , Custom IC Design , modgens , Virtuoso Layout Suite , Custom IC

System, PCB, & Package Design 

IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

When you need to make an edit to a component, whether that is the BGA footprint in…

• 8 min read
Allegro Package Designer

Breakfast Bytes

A Big Problem with Big Data

I happened to read a blog post that referred to a 2018 paper in The Annals of Applied…

• 5 min read
deep learning , big data
CDNS - Fix Layout Hompage