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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

AImotive: Shifting Gear in Automotive

At the recent Cadence Automotive Design Summit, Laszlo Kishonti, CEO of AImotive…

• 5 min read
Automotive , autonomous driving , ADAS

Breakfast Bytes

Mary Meeker: Security, Gigs, Healthcare, China

This is the third (of three) posts about Mary Meeker's 2019 report on Internet Trends…

• 8 min read
mary meeker , Internet

Breakfast Bytes

Mary Meeker: Fulfillment, News, and Money

This is the second post (of three) about Mary Meeker's 2019 report on Internet Trends…

• 5 min read
mary meeker , Internet

Whiteboard Wednesdays

Whiteboard Wednesdays - Inductance Extraction for Digital Designs

In this week’s Whiteboard Wednesdays, Cadence expert Varun Raj Garapati explains…

• less than a min read
Whiteboard Wednesdays , Inductance Extraction , Quantus

System, PCB, & Package Design 

IC Packagers: Six Steps of IC Packaging

Do you want to create an IC Package and are on the lookout for a tool that suits…

• 5 min read
APD , IC Packaging & SiP design , SiP Layout

System, PCB, & Package Design 

BoardSurfers - Aerials and Bails: How to Rename Reference Designators Using Batch…

Components on a board are often placed per their functional group and hence their…

• 2 min read
PCB Editor , Allegro PCB Editor

Breakfast Bytes

Mary Meeker: How Much Is the Internet Growing?

Every year Mary Meeker produces a big presentation on Internet Trends. And when I…

• 6 min read
mary meeker , Internet , mobile

Breakfast Bytes

Automotive Industry Basics

A couple of weeks ago Cadence held its second Automotive Design Summit here on the…

• 8 min read
Automotive , tier-1 , automotive oem , autonomous driving , ADAS , tier-2

Breakfast Bytes

Sunday Brunch Video for 4th August 2019

https://youtu.be/5b0hczb-5FI Made at building 11 (camera Sean) Monday: Ludwigsburg…

• less than a min read
sunday brunch

Breakfast Bytes

My Boris Johnson Story

Boris Johnson is the new Prime Minister of Britain. Unlike most people who rise in…

• 3 min read
the spectator , great britain

Computational Fluid Dynamics

CREMHyG Analyzes Transient Flow in a Multi-Piston Pump Design

Author: Claude Rebattet, Head of CREMHyG laboratory, University of Grenoble Alpes…

• 5 min read
piston pump , Hydraulic , Computational Fluid Dynamics , engineering , simulation software , NUMECA , CREMHyG

PCB、IC封装：设计与仿真分析

Cadence Clarity为系统分析和设计提供前所未有的性能及容量

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“ Bringing Clarity to System Analysis…

• less than a min read
Chinese blog , CDNLive , 电磁场仿真 , 3D EM仿真 , 中文 , 系统级分析 , cdnlive china , 3D分析 , Clarity 3D Solver , 3D建模 , clarity

System, PCB, & Package Design 

3D EM Simulation Is Necessary

Accurate 3D EM simulation is increasingly necessary as data rates increase. For example…

• 2 min read
CDNLive , system analysis , 3D analysis , CDNLive 2019 , 3D EM simulation , CDNLive San Jose , Clarity 3D Solver

Analog/Custom Design

Virtuosity: Automated Device Placement and Routing - Identifying Device Groups and…

This blog highlights the importance of identifying device groups and topologies in…

• 2 min read
ICADVM18.1 , Automated Device-Level Placement and Routing , VPR , Automatic Placement , Advanced Node , Virtuoso Placer , Layout EXL , APR , Auto P&R , Virtuoso , Virtuosity , Virtuoso Placement , Custom IC Design

Breakfast Bytes

CHIPs: Interns Around the World

Cadence has an intern program that goes under the name CHIPs, for college hires and…

• 3 min read
Interns , Cadence Academic Network

System, PCB, & Package Design 

IC Packagers: Multi-Wire Bonding with Ease Using Cadence IC Packaging Tools

When wire bonding, the most common situation remains a single wire from pin to finger…

• 5 min read
APD , wirebonds , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Capturing Design Intent for Automatic Routing in PCB Editor

Imagine you are designing a complex board with thousands of interconnects and all…

• 2 min read
PCB Editor

Breakfast Bytes

IEEE Unified Power Models

Today the IEEE announced the release of IEEE 2416-2019, a standard for unified power…

• 5 min read
Low Power , Si2 , ieee 2416 , thermal , power

Whiteboard Wednesdays

Whiteboard Wednesdays – xSPI Standard Explained

In this week’s Whiteboard Wednesdays video, Jacek Duda explains the xSPI standard…

• less than a min read
Whiteboard Wednesdays , xSPI , JEDEC
CDNS - Fix Layout Hompage