Explore the Cadence Community Forums to find and exchange in-depth technical information.

Featured

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now…

At CDNLive EMEA, Zhan Gao presented her results on cell-aware test. This is the paper…

• 4 min read
Cadence Academic Network , modus , imec , cell-aware test

Breakfast Bytes

Ericsson Using Virtual Platforms for Dynamic Analysis

At CDNLive EMEA last month, Ola Dahl of Ericsson presented Dynamic Software Analysis…

• 4 min read
CDNLive , virtual platform , CDNLive EMEA , Ericsson

Academic Network

Europractice and Cadence – A Long Fruitful Partnership

Those who have studied microelectronics in Europe since 1989 have certainly heard…

• 3 min read
Europractice , Cadence Academic Network , university program

Verification

Specman: Python Is here!

Do you know from where Python technology gets its name? It is not from the snake…

• 3 min read
Specman/e , Python , Specman e , machine learning , specman elite

Breakfast Bytes

Paris Air Show

Next week it is the Paris Air Show, the biggest trade show in aerospace and defense…

• 4 min read
protium x1 , Aerospace , palladium z1 , Emulation , FPGA prototyping , paris air show

Whiteboard Wednesdays

Whiteboard Wednesdays - Cadence Cloud - Fast, Painless, Proven Solutions for Cloud…

In this week's Whiteboard Wednesdays video, Tom Hackett continues his discussion…

• less than a min read
Whiteboard Wednesdays , Cloud-based Design , cadence cloud

System, PCB, & Package Design 

IC Packagers: A Classic Revisited - Ball Map Spreadsheets

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google,…

• 4 min read
APD , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Text Labels and Film Views Help Intelligent Designers

Last time, I talked about color and visibility as it relates to simplifying your…

• 5 min read
APD , Allegro Package Designer , Allegro PCB Editor , SiP Layout

Breakfast Bytes

Making Trouble in Las Vegas

For years John Cooley has organized what is called the Cooley's DAC Troublemaker…

• 10 min read
DAC , troublemaker , 56dac

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes - Using Finish Trunk

The first blog of the series talks about features that are not new but capabilities…

• 4 min read
Trunk Trimming , Pin to Trunk , Create Wire , space-based router , Virtuoso Space-based Router , layout XL , Layout Suite , Trunk Extending , Layout L , Finish Trunk , EM Trunk Optimization , Custom IC Design

Learning and Support

Single-Stop Learning Resource for Cadence Low Power Simulation

Since 2006, low power design has evolved from simple shut off and isolation to very…

• 2 min read
low power simulation , LPS , suppport , power

Breakfast Bytes

Cadence Cloud Passport Partner Program

Last year at DAC, Cadence announced Cadence Cloud (see my post Cadence Cloud from…

• 6 min read
passport partner program , cadence cloud

Breakfast Bytes

Sunday Brunch Video for 9th June 2019

https://youtu.be/T8nSP-oElJM Made at Design Automation Conference (camera Sean)…

• less than a min read
sunday brunch

SoC and IP

SemiEngineering Article: Why IP Quality Is So Difficult to Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part…

• 3 min read
IP , cadence , IP blocks , Automotive Ethernet , ip cores , Tensilica , semiconductor IP , Design IP and Verification IP

PCB、IC封装：设计与仿真分析

线下专家培训第二站：PCB高效设计入门到进阶——第一期之设计环境准备

前言 大家好，我是Principal Customer Engagement Engineer郑凤仙，从事PCB设计行业十六年，先后受聘于Mitac、华为两家企业…

• less than a min read
PCB , 设计习惯 , 设计经验 , Chinese blog , 经验分享 , 设计总结 , PCB设计 , 设计环境 , 中文 , 专家培训

Academic Network

Carnegie Mellon University – Real World Engineering Program

Cadence San Jose was happy to host a group of undergraduate students from Carnegie…

• 1 min read
young professionals , cmu , Academic Network , university program

Analog/Custom Design

Virtuoso Video Diary: Can I Put Sticky Notes on Nets When Resolving EM Violations…

Do you know the Virtuoso Electrically Aware Design flow provides a sticky notes-kind…

• 2 min read
ICADV12.3 , ICADVM18.1 , EM/IR , electrically-aware design flow , Layout EAD , Virtuoso Layout EXL , Virtuoso , IC6.1.7 , IC6.1.8 , Virtuoso Layout Suite XL

Breakfast Bytes

1984 Was Published 70 Years Ago

If you work in any aspect of tech, one book that you have to have read is George…

• 4 min read
george orwell , 1984

Academic Network

Cadence Academic Network Expands to Kazakhstan

Dear reader, may I ask you, what do you know about Kazakhstan ? Do you know that…

• 2 min read
university , Cadence Academic Network , Kazakhstan
CDNS - Fix Layout Hompage