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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

DDR5 Is on Our Doorstep

The talk of the town in the DRAM market (well, apart from its growth in the last…

• 3 min read
OIP , ddr5 , DDR4 , Micron , TSMC , DRAM

Breakfast Bytes

ESD Alliance Workshop on Digital Marketing: Tools and Sales

Yesterday was the first part about the ESD Alliance Digital Marketing workshop. Today…

• 3 min read
digital marketing , onespin , esd alliance

Spotlight Taiwan

Snapshots of CDNLive Taiwan 2018

Taiwan is one of the most important hubs for the global semiconductor industry. Served…

• 3 min read
Taiwan , CDNLive , cdnlive taiwan

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之7：梯形凸块布线——下一代高速布线解决方案

通过梯形凸块布线高效利用布线通道 梯形凸块布线是一种新方法，可以通过在并行走线上添加梯形形状来控制引脚区域或者突破区域的阻抗，减少开放区域的串扰。这是一个突破性的布线策略…

• less than a min read
PCB , Chinese blog , Allegro 17.2 , 布线 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro升级17.2 , 高速

Breakfast Bytes

ESD Alliance Workshop on Digital Marketing: Agility

Last week the ESD Alliance ran another workshop on digital marketing, with Nicolas…

• 5 min read
digital marketing , onespin , esd alliance

SoC and IP

NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

Trust. Privacy. Confidentiality. These are three important concerns for designers…

• 1 min read
IP , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things

Breakfast Bytes

Azure for Silicon Design with Cadence and TSMC

I used to live on the Cote d'Azur, which is what everyone else calls the French Riviera…

• 4 min read
OIP , microsoft , TSMC , azure , cadence cloud

Whiteboard Wednesdays

Whiteboard Wednesdays - Tensilica Neural Network Compiler: An Offline Tool for Efficient…

In this week’s Whiteboard Wednesda ys video, Megha Daga describes how the Tensilica…

• less than a min read
DSP , Whiteboard Wednesdays , Tensilica , neural networks , AI

System, PCB, & Package Design 

How To Maintain Connectivity in a Multiboard PCB System

By John Burkhert Jr Bringing a multiboard system together is a chance for the designer…

• 7 min read
PCB , allegro edm , multi-board , System-Level Design , Allegro PCB Designer Team Design Option , multiboard , system , PCB design , pcb system , Allegro

Breakfast Bytes

David White and Machine Learning

Recently Cadence held a worldwide event for our interns. To read more about our intern…

• 6 min read
artificial intelligence , machine learning , David White , neural networks

Verification

Improving Your Testbench Flexibility with Enhanced Specman Templates

Cadence® Specman® Elite delivers faster and higher quality verification at block…

• less than a min read

Verification

Specman 18.09: Avoiding the Small Annoying Mistakes

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one…

• 2 min read
enumerator , Specman , Functional Verification , e , e language , specman elite , xcelium

Verification

App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Object…

Welcome back to the fourth installment of a special multi-part edition of the App…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Analog/Custom Design

Virtuoso: The Next Overture - Virtuoso RF Solution for High Frequency Product De…

The latest Advanced Methodology Virtuoso release (ICADVM18.1) introduces Virtuoso…

• 4 min read
Virtuoso Overture , custom/analog , Virtuoso New Design Platform , VRF , vsdp , Virtuoso , RF design , Custom IC , Virtuoso Layout Suite XL

Breakfast Bytes

History of ISO 26262

I have known Kurt Shuler, the VP marketing at Arteris, for some time. But this post…

• 5 min read
Arteris , ISO 26262 , ADAS , iso 21448 , Breakfast Bytes

PCB、IC封装：设计与仿真分析

基于团队协作的AC/DC电源完整性设计与分析方法

在与用户的交流中，我们收获了许多问题与建议：如何使用压降分析或AC分析技术、如何改进PCB设计流程、如何优化去耦电容的使用等等……这些问题推动着我们不断完善电源和信号完整性的设计…

• less than a min read
PCB , DC , PI , Chinese blog , 电源完整性 , 团队协作 , Power Integrity , 约束驱动的PCB设计流程 , ac , PCB设计 , 中文 , PowerTree , Sigrity , 压降分析 , 约束驱动

Breakfast Bytes

TSMC OIP Ecosystem Forum

Last Wednesday was the TSMC OIP Ecosystem Forum. The first part of the day was hosted…

• 5 min read
OIP , 7nm+ , TSMC , 5nm , 7nm

Breakfast Bytes

EXTRA: Did the Chinese Really Attach Rogue Chips to Apple and Amazon's Motherboards…

Today, Bloomberg's BusinessWeek (BW from now on) published a story The Big Hack:…

• 6 min read
security , Apple , China , Amazon

Breakfast Bytes

PCB West: History of PCB

At PCB West recently, Wally Rhines gave one of the keynotes. It was titled Is Past…

• 8 min read
PCB , cadence , Wally Rhines , Valid , printed circuit board , Mentor
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