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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Dual Channel DIMMs for Server Applications

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty, discusses how future…

• less than a min read
Whiteboard Wednesdays , Dual Channel DIMM , DIMM

Analog/Custom Design

Integrating AMS IP in SoC Verification Just Got Easier

Typically, analog designers verify their AMS IP in schematic driven, interactive…

• 1 min read
AMS , mixed signal solution , Mixed-Signal , analog/mixed-signal , Virtuoso , mixed signal , Virtuoso environment , mixed-signal verification

Breakfast Bytes

Fooling Neural Networks

I wrote recently about various aspects of modeling , not just transistor models,…

• 4 min read
security , neural networks , CNN

Breakfast Bytes

The Old Order Changeth: Samsung Takes the Crown

The most famous line of Tennyson's poem Morte D'Arthur is "The old order passeth…

• 6 min read
Intel , Memory , flash , Samsung , mobile

Analog/Custom Design

Virtuosity: Sharing Custom SKILL Calculator Functions

Have you ever written a fantastic piece of SKILL to carry out a calculation and wanted…

• 3 min read
Analog Design Environment , ADE Explorer , Virtuoso , ViVA , Custom IC Design , SKILL , ADE Assembler

Breakfast Bytes

DesignCon: PCB and Packaging Take Center Stage

You wouldn't really know it from the name, but DesignCon is all about the design…

• 8 min read
si/pi , EMI , DesignCon , deep learning , Power Integrity , machine learning , Signal Integrity , dnn , CNN , neural network

Verification

New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant…

• 2 min read
amba5 , ACE5 , AXI5 , AMBA

Breakfast Bytes

DesignCon: SI, PI and EMI Have a Threesome

DesignCon 2018 opened with a keynote panel on the subject of SI, PI, and EMI Challenges…

• 8 min read
DesignCon , Power Integrity , Signal Integrity , electromagnetic interference

SoC and IP

You Won't Believe Your Ears When Listening to Your Laptop

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth…

• 2 min read
CES , audio , HiFi , Tensilica

Breakfast Bytes

Open-Source IP in Government Electronics

At the RISC-V conference late last year, one of the keynotes was by Linton Salmon…

• 6 min read
risc-v , dod , darpa

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4X DRAM: Performance and Power Efficiency Improvements…

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty will help you learn…

• less than a min read
Whiteboard Wednesdays , LPDDR4

Breakfast Bytes

All Models Are Wrong; Some Are Useful

"All models are wrong, some are useful.” This remark is attributed to the statistician…

• 9 min read
climate , model , digital , SPICE

Verification

JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive…

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification…

• 1 min read
Verification IP , UniPro , MIPI Alliance , JEDEC , automotive electronics , UFS , storage , MPHY

Breakfast Bytes

TSMC 30 Years Ago Today

At IEDM in December, Gary Dagastine is one of the people responsible for press relations…

• 6 min read
Taiwan , fabless , TSMC , chips and technologies , foundry

The India Circuit

The Promise Of Digital India

By 2019, it is estimated that there will be five billion mobile phone users in the…

• 4 min read
Narendra Modi , digital india , National Digital Literacy Mission , Aadhar , Ravi Shanker Prasad

Breakfast Bytes

City Slickers Marketing

Last week I talked about sales in Running a Salesforce . This week it is the turn…

• 4 min read
steve blank , city slickers marketing , marketing

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Challenges for SoCs Integrating CCIX Interface…

In this week's Whiteboard Wednesdays episode, Nick Heaton, Distinguished Engineer…

• less than a min read
Whiteboard Wednesdays , ccix

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE/Marine for various…

• 3 min read

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE /Marine for various…

• 4 min read
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