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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

IEEE Elects EDA Professional as President

When I lived in England, newspapers had a tradition of not mentioning other newspapers…

• 4 min read
Karen Bartleson , EDA standards , Electronic design , IEEE

Breakfast Bytes

Weekly News—October 16, 2015

Largest Tech Merger Ever Earlier in the year Avago announced that it was acquiring…

• 2 min read
Intel , Dell , 5nm test chip , imec , EMC , Qualcomm , Breakfast Bytes , Weekly News

Breakfast Bytes

Goldilocks and the Three Ways

The two obvious ways to implement a complex algorithm are to write a large amount…

• 4 min read

Breakfast Bytes

Memory and Storage: the Wall is Coming Down

It was MemCon this week. Three keynotes, three parallel tracks each with four presentations…

• 4 min read
IP , Memory , MemCon , storage , DRAM , flash memory

Breakfast Bytes

Rules for Radicals: Practical Advice for Adopting Formal

This year's Jasper User Group conference finished up with a dose of realism in a…

• 4 min read
Jasper User Group , JUG , formal , PMC Sierra , Imagination , Jasper , broadcom , Qualcomm , Paul's Posts , Formal verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Automotive IP Subsystems

In this week's Whiteboard Wednesdays video, Charles Qi takes a closer look at IP…

• less than a min read
Automotive , Whiteboard Wednesdays , IP , subsystem

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Symbol Editor? 16.6 Has a Couple of New Enhancements…

The Allegro PCB Editor release has a few new capabilities related to symbol pins…

• 1 min read
Allegro GUI , Allegro 16.6 , SPB , PCB Editor , PCB design , Grzenia , Allegro PCB Editor , library , Allegro

SoC and IP

Cadence Ports LPDDR4/DDR4 Combo PHY to TSMC 28HPC to Serve Rapid Adoption in Consumer…

Rapid consumer product revolution continues to be enabled by semiconductor technology…

• 1 min read
DDR4 , LPDDR4 , MemCon , LPDDR , DDR , DDR3 , LPDDR3

Breakfast Bytes

Batterygate, the Scandal that Isn't

If you think power isn’t important then you must have been living under a rock for…

• 5 min read
Apple , Samsung , TSMC , Paul's Posts , power

Breakfast Bytes

Thanks for the Memory: How MemCon Got Started

It is MemCon on Tuesday. I talked to David Lin to find out how it all started. He…

• 3 min read
DDR2 , Memory , DDR4 , MemCon , flash , JEDEC , NAND flash , ddrx , DRAM , nor flash , DDR3

Breakfast Bytes

Weekly News, October 9th, 2015

TSMC and Samsung Both in iPhone 6s It emerged that for the Apple iPhone 6s and…

• 2 min read
Intel , 5nm test chip , Altera , imec , PMC-Sierra , iPhone 6s

Breakfast Bytes

Jasper: the Gold Standard for Formal Verification

It was the Jasper User Group JUG this week. I first went to JUG several years ago…

• 4 min read
Jasper User Group , JUG , Jasper , Paul's Posts , Formal verification

SoC and IP

USB Developer Days – Turning Specifications into Applications

Each time I start working on an introductory paragraph for a new USB blog entry,…

• 2 min read
USB 3.0 , cadence , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Breakfast Bytes

Cadence and imec Announce World's First 5nm Tapeout

7nm is already passé it seems! Today Cadence and imec announced the tapeout of the…

• 4 min read
testchip , imec , Innovus , 5nm , 7nm , SAQP , EUV

Breakfast Bytes

The Beginning of Breakfast Bytes

Yes, it’s true. The Cadence gravitational field finally pulled me back and I am now…

• 1 min read
Paul McLellan , DAC , Jasper User Group , VSLI

Whiteboard Wednesdays

Whiteboard Wednesdays—New Tensilica Vision P5 DSP

In this week's Whiteboard Wednesday video, Dennis Crespo highlights the performance…

• less than a min read
security , Automotive , DSP , Vision P5 , Whiteboard Wednesdays , IP , Tensilica , mobile

SoC and IP

Ethernet Reaches into Ever More Application Spaces

I blog from time to time about what’s new in Ethernet. I have just returned from…

• 2 min read
HDD , 802.3bs , Automotive Ethernet , Ethernet , Design IP and Verification IP , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays—Meeting Automotive Memory and I/O Bandwidth Challenges

In this week's Whiteboard Wednesdays video, Charles Qi continues his discussion focused…

• less than a min read
Automotive , I/O , Whiteboard Wednesdays , IP , Memory , interfaces , bandwidth , high performance

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Pastemask DRC? 16.6 Has Several New Enhancements…

The Allegro PCB Editor 16.6 Pastemask to Pastemask DRC now checks the ‘Package Geometry…

• less than a min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro
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