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SoC and IP

16Gbps Multi-link, Multi-protocol SerDes at the 21st IEEE European Test Symposiu…

The 21 st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands…

Steve Brown 1 Jun 2016 • 1 min read

16gbps , PCIe Gen4 , SerDes , Multi-link , multi-protocol

Academic Network

DAC 2016—Student Activities and Scholarships

The Cadence Academic Network is the proud sponsor of all student activities and scholarships…

susarla 31 May 2016 • 2 min read

DAC , Cadence Academic Network , dac53 , Design Automation Conference , 53dac

Analog/Custom Design

Virtuoso Video Diary: Tips and Tricks on Virtuoso Visualization and Analysis XL …

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

Ashu V 31 May 2016 • 6 min read

custom/analog , Analog Simulation , analog , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Breakfast Bytes

DAC: the Curtain Rises on the Cadence Theater

As in previous years, a highlight of the Cadence booth at DAC is the theater, where…

Paul McLellan 31 May 2016 • 4 min read

DAC , Cadence Academic Network , Cadence Theater , dac53 , Design Automation Conference , 53dac

SoC and IP

What Memory Best Fits Your Application?

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know…

Steve Brown 27 May 2016 • 1 min read

DDR4 , LPDDR4 , 4266 , 3200

Breakfast Bytes

Breakfast Bytes: Post #150

This is the 150th blog post here at Breakfast Bytes since I arrived at Cadence in…

Paul McLellan 27 May 2016 • 3 min read

IP , EDA , Semiconductor , Breakfast Bytes

Breakfast Bytes

3D Xpoint: Is It a Game-Changer?

You have probably at least heard of 3D Xpoint. This is a memory technology jointly…

Paul McLellan 26 May 2016 • 4 min read

Intel , Memory , Micron , flash , memory hierarchy , 3dx , DRAM , Breakfast Bytes , 3d xpoint

System, PCB, & Package Design

What's Good About the Latest in ADW? The 16.6-2015 Release Has Several New Enhancements…

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new…

Jerry GenPart 25 May 2016 • 2 min read

PCB , Cadence Design Systems , Allegro Design Workbench , Library and design data management , Grzenia , Librarians , library , ADW

Breakfast Bytes

Andrew Kahng on Industry-Academia Cooperation

At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled…

Paul McLellan 25 May 2016 • 4 min read

ucsd , Cadence Academic Network , CDNLive , academia , kahng , CDNLive Silicon Valley

SoC and IP

Continued Strength of the Design&Reuse IP-SoC India

Design&Reuse events are always exciting for their draw of an IP-centric audience…

Steve Brown 25 May 2016 • 1 min read

PCIe Gen4 , 10G-KR , SerDes

Verification

Simulation Acceleration—Maximizing Simulator Performance

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to…

teamspecman 25 May 2016 • 4 min read

Specman , Functional Verification , e , specman elite , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Creating an Acceleration-Ready Simulation Environment with…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated…

References4U 24 May 2016 • less than a min read

accelerated VIP , Verification IP , Whiteboard Wednesdays , IP , VIP , Palladium XP , simulation , SystemVerilog UVM , verification

Breakfast Bytes

CDNLive: Routing at 10nm

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence…

Paul McLellan 24 May 2016 • 3 min read

CDNLive , Routing , implementation , 10nm

Breakfast Bytes

What Is RocketSim? Why Did Cadence Acquire Rocketick?

I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick…

Paul McLellan 23 May 2016 • 3 min read

dac2016 , gate-level simulation , DAC , Functional Verification , NVIDIA , RTL simulation , Incisive , dft simulation , rocketick , rocketsim , intel capital , Breakfast Bytes

Breakfast Bytes

Linley IoT Conference: Security and...Well, Just Security

Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago.…

Paul McLellan 20 May 2016 • 5 min read

security , IoT , industrial , Linley , wearables , Internet of Things , power , consumer , Breakfast Bytes

Breakfast Bytes

It's HOT in Austin in June

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held…

Paul McLellan 19 May 2016 • 2 min read

dac2016 , DAC , CASEA , HOT , Heart of Technology , Jim Hogan , Breakfast Bytes

Breakfast Bytes

Party Like It's 1999—How the Denali Party Started

As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever…

Paul McLellan 18 May 2016 • 3 min read

dac2016 , DAC , Denali Party , disco inferno , Denali , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Modular VIP Architecture

In this week's Whiteboard Wednesdays video, Liron Stoler describes how the Cadence…

References4U 17 May 2016 • less than a min read

Verification IP , Whiteboard Wednesdays , IP , VIP , system-level verification , block-level verification , modular architecture

Breakfast Bytes

CDNLive EMEA: Memories Are Made of This

At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory…

Paul McLellan 17 May 2016 • 4 min read

LPDDR , CDNLive EMEA , memory IP , DDR , memory interface IP

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