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Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Made Easy with Memory Models

In this week's Whiteboard Wednesdays, Tom Hackett explains memory models and their…

References4U 19 Aug 2014 • less than a min read

Whiteboard Wednesdays , wide i/o , SoC , memory models , verifying memory interfaces

SoC and IP

Highlights from Recent IEEE 802.3 Ethernet Standards Meeting

I wanted to share with you a number of updates from last month's IEEE 802.3 meeting…

ArthurM 18 Aug 2014 • 2 min read

25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet

System, PCB, & Package Design

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

The signal integrity (SI) prophets had predicted this time would come, and it turns…

TeamAllegro 14 Aug 2014 • 4 min read

Serial link analysis , DDR4 , BER Analysis , SystemSI , Power aware SI , Allegro Sigrity

Verification

Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the…

Chinmay 13 Aug 2014 • 2 min read

SystemVerilog , uvm , profiling , Incisive , post-simulation profiling , verification

SoC and IP

IoT Focus: Natural User Interface Design Crucial to Success

Each era of electronics innovation is generally marked by a dominant end application…

Seow Yin Lim 13 Aug 2014 • 2 min read

Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Whiteboard Wednesdays

Whiteboard Wednesdays - How to Support Higher Performance Multimedia Applications…

In this week's Whiteboard Wednesdays, Charles Qi continues his discussion on hosted…

References4U 12 Aug 2014 • less than a min read

Whiteboard Wednesdays , IP , hosted virtual desktop , user inputs processing , virtualized device enumeration , USB controllers , multimedia

System, PCB, & Package Design

What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!

Just a brief post this week to mention a new capability for Allegro Design Entry…

Jerry GenPart 12 Aug 2014 • less than a min read

Allegro Design Entry , Allegro 16.6 , 16.6 , SPB , Design Entry HDL , PCB design , Design Entry

Verification

Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption…

The state-of-the-art Palladium XP hardware/software verification computing platform…

SumeetAggarwal 7 Aug 2014 • 2 min read

ICE , sim accel , IXCOM , Palladium XP , COS Cadence Online Support , Simulation acceleration , hsv , RAKs , stb

Whiteboard Wednesdays

Whiteboard Wednesdays - The Evolution of NAND Flash

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need…

References4U 5 Aug 2014 • less than a min read

Whiteboard Wednesdays , IP , BCH algorithm , NAND flash , error correction

Verification

Verification IP: 7 Things I Learned By Browsing Cadence Online Support Last Mont…

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more…

SumeetAggarwal 4 Aug 2014 • 4 min read

Verification IP , IVD , Cadence app notes , MDIO Interface , VIP , Cadence Online Support , DpDm , SOMA to UVM Configuration

System, PCB, & Package Design

Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting…

Manufacturability and quality of the power and ground feeds for your package are…

Jeff Gallagher 31 Jul 2014 • 2 min read

SiP , IC Package , 16.6 , APD , package design , Allegro Package Designer

Verification

New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog…

There is always a demand for learning something simply and quickly on your own in…

SumeetAggarwal 30 Jul 2014 • 3 min read

SystemVerilog , Verification IP , uvm , GMII , Rapid Adoption Kit , VIP , M-PCIe , RAK

Whiteboard Wednesdays

Whiteboard Wednesdays - Defining Different Types of USB Controllers

In this week's Whiteboard Wednesdays, Jacek Duda takes a closer look at different…

References4U 29 Jul 2014 • less than a min read

Whiteboard Wednesdays , host , bus , USB controllers , peripheral devices , hub

SoC and IP

Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since…

Arif Khan 29 Jul 2014 • 1 min read

PCIe controller , PCIe IP , PCIe low power , PCIe , PCIe PHY

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

Cadence Online Support, https://support.cadence.com/ , provides access to support…

SumeetAggarwal 28 Jul 2014 • 5 min read

COS , IMC , SystemVerilog , random stability , LPS , UVM-ML , CPF , debugging tips , Cadence Online Support , UVM ML , troubleshooting , irun , IES , vManager