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Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to…

Hiro Ishikawa 28 Jan 2013 • 6 min read

STI , Virtuoso Advanced Node , length of diffusion , custom/analog , Routing , analog prototyping , Double Patterning , layout-dependent effects , Ishikawa , custom , odd-loop marker , 20nm , Advanced Node , module generation , analog , WPE , design flow , LDE , dynamic coloring , LOD , well proximity , Placement , stress , interconnect layers , Custom IC Design , local interconnect

Verification

A Concrete Linux Virtual Platform Example

Virtual platforms are used to find many different types of system and software issues…

jasona 25 Jan 2013 • 3 min read

Device Drivers , zynq , virtual platforms , virtual prototypes , UART , embedded software , Ubuntu , softtware bugs , SystemC , xilinx , Zynq virtual platform , debugging software , linux , Jason Andrews , Zynq-7000 , System Design and Verification

Verification

A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True…

It is January 2013, the year has begun and it is time for my annual 10 year look…

fschirrmeister 23 Jan 2013 • 4 min read

SystemVerilog , Apple , Low Power , integration , Google Glass , virtual platforms , tungsten , GPS , Cell Phone , base stations , MP3 , virtual prototypes , IBM , Harry Goldstein , PDA , abstraction , google , Linda Geppert , 10 year , Palm , hardware/software CoDesign , 10 year look-back , software , IEEE Spectrum , Mark. E. Dean , Schirrmeister , ESL , iPhone , ESL system-level design

System, PCB, & Package Design

What's Good About DEHDL’s Interface Aware Design? The Secret's in the 16.6 Release

Components in a design communicate with each other based on some rules or protocols…

Jerry GenPart 21 Jan 2013 • 3 min read

interface aware design , PCB , PCB Layout and routing , constraints manager , Allegro 16.6 , DEHDL , signal grouping , hierarchical net groups , 16.6 , interface definitions , interfaces , PCB Editor , Design Entry HDL , PCB design , Grzenia , net groups , Allegro

Verification

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually…

teamspecman 21 Jan 2013 • 2 min read

AF , IntelliGen , Specman , debug , Functional Verification , garbage collection , lists , Incisive , e code , Generation , e language , assumed generation , Funcional Verification , Zander , vManager , random generation

System, PCB, & Package Design

Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD

Documentation is key when completing any IC package substrate design. Without it…

Jeff Gallagher 17 Jan 2013 • 3 min read

package , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , APD 16.6 , Physical layout and co-design

Verification

2013 CES: Top 4 Trends Benefiting EDA

While a variety of EDA customer segments are growing, consumer electronics continues…

jvh3 17 Jan 2013 • 5 min read

Automotive , mobile devices , Verification IP , Design IP , Joe Hupcey III , IP , Consumer Electronics Show , CES , 14nm , SoC , apps , UltraHD TVs , verification

System, PCB, & Package Design

What's Good About Viewing Constraint Differences? See for Yourself in Allegro 16

Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint…

Jerry GenPart 16 Jan 2013 • 2 min read

PCB , PCB Layout and routing , constraint databases , Allegro 16.6 , 16.6 , PCB Editor , viewing constraint differences , constraint difference , PCB design , Constraints , Grzenia , comparing constraints , Allegro PCB Editor , Allegro

Digital Design

Five-Minute Tutorial: Creating An EM Model File

One of the least-fun parts of running power and rail analysis has always been coming…

Kari 14 Jan 2013 • 2 min read

EDI , electromigration , rail analysis , EM Model , ICT , iRCX , EPS , Power Analysis , five minute tutorial

Analog/Custom Design

Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

In addition to the R&D engineers who actually develop our software, the folks in…

stacyw 14 Jan 2013 • 4 min read

Variability Aware Design , AMS , Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , VSR , Analog Simulation , Cadence Space-based Router , workshop , IC615 , IC 6.1.5 , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ViVA , ADE-XL , mixed signal , Custom IC Design , Virtuoso Layout Suite

Analog/Custom Design

Library "Safe Margins" -- Are They Really Saving Your Design?

Designers need to radically re-think their strategies for timing closure to get the…

AElzeftawi 10 Jan 2013 • 4 min read

Standard Cell , memory characterization , Process Variation , Elzeftaki , library characterization , Timing Closure , Complex IO , PVT corners , safe margins , Complex Cell

Analog/Custom Design

SKILL for the Skilled: Part 6, Many Ways to Sum a List

In a previous post I presented sumlist_2b as a function that would sum lists of length…

Team SKILL 10 Jan 2013 • 5 min read

Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design

Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and PCB …

Placement and routing have always been an integral part of printed circuit board…

Naveen 9 Jan 2013 • 4 min read

capture , "capture CIS" , SPB16.3 , Allegro Design Entry , Allegro 16.6 , customer support , PCB design" , net swap , Design Entry CIS , OrCAD Capture Marketplace , Routing , OrCAD Capture , 16.6 , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , Allegro 16.5 , Allegro 16.2 , SPB16.2 , Appnote , pinswap , "PCB design" , OrCAD , swap , 16.5 , Design Entry , SPB16.5 , Allegro PCB Editor , pin swap , application note , OrCAD PCB Editor , library , PCB Capture , Schematic

Analog/Custom Design

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitmen…

Cadence holds a leading position in the EDA industry due to its broad product portfolio…

Sathish Bala 8 Jan 2013 • 1 min read

CDNLive , cadence , AMS Designer , custom , Design Challenges , analog , web page , Mixed-Signal Methodology Guide , Mixed-Signal , Mixed-signal solutions web page , Virtuoso , mixed-signal book , digital , implementation , mixed signal , Encounter Digital Platform , web site , verification

Verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

teamspecman 1 Jan 2013 • 7 min read

AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS

Verification

System Design 2012 – Real Users Achieving Real Results!

This morning the final success story my team has been working on for this year went…

fschirrmeister 21 Dec 2012 • 4 min read

ESL Market , Nufront , Altair , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Sigma , Acceleration , Functional Verification , LeCroy , Dynamic Power Analysis , Doulog , System Design and Verification , Freescale , Methods2Business , System Development Suite , Samsung , embedded software , Rohde & Schwarz , Ericsson , LSI , Palladium XP , Emulation , CSR , CDNLive! , ST Microelectronics , Texas Instruments , xilinx , DAC 2012 , ARM , Schirrmeister , Accelerated Verification IP , low power optimization

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2

Greetings, Simulating crystal oscillators got a lot easier in MMSIM12.1... We…

Tawna 20 Dec 2012 • 5 min read

RF , RF Simulation , analog/RF , APS , Circuit simulation , Virtuoso Spectre , HB , Spectre RF , Analog Simulation , MMSIM , Virtuoso Spectre Simulator GXL , MMSIM 12.1 , analog , Analysis , ADE , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , VCO , crystal oscillator , Oscillator , simulation

System, PCB, & Package Design

Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in…

For most IC package designers, the GDSII format is a part of daily life. You may…

Jeff Gallagher 20 Dec 2012 • 5 min read

SiP , IC Package , IC Packaging , GDSII , packaging , cadence , Digital SiP design , stream , 16.6 , GDS-II , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , APD 16.6 , SiP Layout , Physical layout and co-design

RF Engineering

Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 1

Greetings! Simulating Crystal Oscillators got a lot easier in MMSIM12.1... We…

Tawna 19 Dec 2012 • 8 min read

RF , RF Simulation , analog/RF , 12.1 , HB , Spectre RF , ADE-L , Analog Simulation , MMSIM , MMSIM 12.1 , analog , RF spectre spectreRF , Virtuoso Spectre Simulator XL , spectreRF , RF design , Circuit Design , harmonic balance , VCO , crystal oscillator , Oscillator

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