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カスタムIC／ミックスシグナル: Start Your Engines: AMSD Flex—Take your Pick! – AMSD Flexモードの紹介

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Start...
- 16 Jun 2020
Breakfast Bytes: Uncanny Valley: Being Human in the Age of AI

Paul McLellan

Today's post is somewhat off-topic, despite having AI in the title. Uncanny Valley: Being Human in the Age of AI is the name of an exhibition at the de Young Museum in Golden Gate Park in San Francisco. I went to see it before we got locked...
- 16 Jun 2020
Verification: Training Insights - Comprehensive RTL Signoff Using JasperGold Superlint App

Nizar Hanna

Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but don't tend to look at their time the same way, ending up wasting this greatly valuable and important resource. You can gain money using time, but you can’t use money to purchase more time.

The …
- 15 Jun 2020
Breakfast Bytes: IEEE 1838: Taking Test into the Third Dimension

Paul McLellan

I've written quite a bit recently about advanced packaging and More than Moore technologies for building systems. For example, see my posts: John Park's Webinar on Chiplets Known Good Die System in Package, Why Now? System in Package, Why No...
- 15 Jun 2020
Breakfast Bytes: Sunday Brunch Video for 14th June 2020

Paul McLellan

www.youtube.com/watch Made in Hakone Japanese Garden, Saratoga (camera Carey Guo) Monday: ETS2020: Functional Safety Tuesday: Take a Cadence Masterclass and Get a Badge Wednesday: Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore) T...
- 14 Jun 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 技巧四：巧用布局技巧

SDA China

多层板设计时，我们肯定都希望能一次性完成完整平面的设计、一次性消除密间距器件的DRC、一次性完成微孔+埋孔协同fanout……本期技巧篇内容将帮助我们轻松达成这些目的。微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接，快快添加收藏吧~ 点击图片可查看清晰大图，点击此处下载PDF版完整内容 “极致PCB设计全流程网课计划”第四期实战直播识别下图二维码，立刻报名！相关内容 ...
- 13 Jun 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 基础四：高质量快速布局

SDA China

布局布线是PCB设计的物理实现环节，在本期内容和接下来的第五期内容中，我们将聚焦于如何利用布局布线规划来减少重复劳动，提升设计效率，将有限的时间用在“刀刃”上。微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接，快快添加收藏吧~ 点击图片可查看清晰大图，点击此处下载PDF版完整内容 “极致PCB设计全流程网课计划”第四期实战直播识别下图二维码，立刻报名！ sp...
- 12 Jun 2020
Life at Cadence: My Life at Cadence Video Series: Chaitra Dustker

Mary Kasik

Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This second video features Chaitra Dustker, lead applications engineer, Digital Implementation. I became interested in e...
- 12 Jun 2020
Breakfast Bytes: Custom Instructions in Tensilica: Wearing a TIE Makes You Smarter

Paul McLellan

Tensilica has a number of different product families targeted at different applications from audio, via video, to deep learning. I've written posts about all of these during the last year. The most recent in each domain were: Audio: HiFi D...
- 12 Jun 2020
System, PCB, & Package Design : Cadence OrCAD and Allegro 17.4-2019 HotFix 007 Is Now Available

AllegroReleaseTeam

The HotFix 007 (QIR 1, indicated as 2020 in the application splash screens) update for OrCAD and Allegro is now available at Cadence Downloads. This release includes many improved product features and new enhancements, mostly resulting from...
- 11 Jun 2020
Digital Design: Library Characterization Tidbits: Understanding the Liberate AMS Command-Line Flow

Jommy

Read to know about the Liberate AMS command-line flow.
- 11 Jun 2020
Breakfast Bytes: Sophie Wilson: The 2020 Wheeler Lecture (Multicore to Today)

Paul McLellan

This is the second post continuing from yesterday's post Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore) covering Sophie Wilson's Wheeler Lecture from Cambridge in the middle of May. Here is the linkfest of the most rece...
- 11 Jun 2020
Learning and Support: Come Join Us for a SystemVerilog Real Number Modeling Seminar!

XTeam

Looking to improve your SystemVerilog? On June 17th, 2020, there’s a webinar going on at 9:00 CEST that can help you out. Come join us for our SystemVerilog Real Number Modeling seminar! You’ve been using device assertions and checks in y...
- 10 Jun 2020
System, PCB, & Package Design : IC Packagers: Welcome to the Dark Side

Tyler

The 7th ISR (HotFix 007 or QIR1) for the 17.4 release is available for download now. This marks the first major update for the 17.4 software stream, and what an update it is! You’ll notice many new things when you download and install the new build. Let’s tal...
- 10 Jun 2020
Analog/Custom Design: Virtuosity: Voltus-Fi-XL FAQ — Your Questions, Our Answers

Pallabi R

Do you want to know the hows and whys of Voltus-Fi? Then don’t miss to get a copy of the Voltus-Fi-XL FAQ document today.
- 10 Jun 2020
Breakfast Bytes: Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore)

Paul McLellan

Since I was an undergraduate studying computer science at what was then called the Cambridge Computer Laboratory, I am on their mailing list. Each year, I get invited to the Wheeler Lecture. But it is normally held onsite at the computer science depa...
- 10 Jun 2020
Breakfast Bytes: Take a Cadence Masterclass and Get a Badge

Paul McLellan

Many of us are locked down, working from home, or at the very least not going to go and sit in a lecture room all day. Not least because that option is probably not available. But one thing you read about almost everywhere you look is that we should ...
- 9 Jun 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Finite Element Can Add Clarity

Amir Asif

This blog helps you explore the features that make Clarity an obvious choice when you need a Finite Element Method-based EM solver for Virtuoso RF Solution.
- 8 Jun 2020
Analog/Custom Design: Virtuosity: The Latest Virtuoso ADE Usability Enhancements

Arja H

Since IC6.1.8/ICADVM18.1 was released we have continued our drive to improve the usability of Virtuoso ADE Assembler, Virtuoso ADE Explorer and Virtuoso Visualization & Analysis. I'll summarize the biggest enhancements in this blog.
- 8 Jun 2020
カスタムIC／ミックスシグナル: Virtuosity: 先端ノード用デバイスレベル配線-Trunk-to-Trunk Mesh配線

Custom IC Japan

トランク（幹線）生成の次のステップは、トランクの相互接続（幹線間接続）です。Virtuoso®デバイスレベル配線のブログシリーズのこのブログでは、新しいTrunk-to-Trunk Mesh配線機能を使ってトランク接続を作成し、EM違反を防ぐ方法について説明します。 Trunk-to-Trunk Mesh配線は、二つ目の配線フローであると言えます。単一のトランクを使用して他のトランクを接続する代わりにグリッド構造またはメッシュ構造のトランクを作成してデザイン内のトランク同士を接続します。...
- 8 Jun 2020
カスタムIC／ミックスシグナル: Virtuosity: デバイスの配置とルーティングの自動化-グリッド生成

Custom IC Japan

Virtuoso®自動デバイスレベル配置およびルーティングシリーズの次の投稿です。最初の投稿では、自動化されたデバイスレベルの配置およびルーティングソリューションの必要性について話しました。 2回目の投稿では、アナログデザインでの非常に重要な手順、「配置と配線のデバイスグループとトポロジの特定」を強調しました。 Virtuosoの自動化されたデバイス配置配線のソリューションがこれらの課題に対してどのように対応しているかを見ました。さぁ、もう少し話を進めてみましょう。今回は、次の需要...
- 8 Jun 2020
PCB設計／ICパッケージ設計: BoardSurfers: 正しさのその先へ – デザイン／配線の改善と最適化

SPB Japan

PCBレイアウトエディタは、設計が正しいことを確認するために、コンストレイント(制約条件)とルールという形式を通じて、多くのチェックを提供します。DFMルールを利用することで、ファブリケーションやマニュファクチャリングの問題も回避できます。さらに、自動配線を使用すれば、正しい接続とトレースを備えたエラーのないボードを確実に設計することができます。ところで、ただ「正しい」というだけのボードに満足できますか？それとも、さらなる改善、最適化を求めますか？また、「クォリティ」についてはどうでしょうか...
- 8 Jun 2020
Breakfast Bytes: ETS2020: Functional Safety

Paul McLellan

One of the keynotes for the European Test Symposium 2020 (ETS2020) was by Cadence's Alessandra Nardi. As you might guess from her name, she's Italian. But I think that's about as European as her presentation got since, instead of coming from Tallinn ...
- 8 Jun 2020
Breakfast Bytes: Sunday Brunch Video for 7th June 2020

Paul McLellan

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: The Five Waves: AI, 5G, Cars, Clouds, IoT Tuesday: TSMC: N7, N6, N5 Wednesday: Artificial Intelligence...and Artificial Performance Thursday: Four More Waves: 5G, Cars, Clouds, IoT F...
- 7 Jun 2020
RF Engineering: Solving RFIC and RF Module Design Issues

Kim Khoury

When creating new RFIC modules, designers typically need an array of tools and applications from various vendors to complete the design process. In 2018, Cadence launched the Virtuoso® RF Solution to enable designers to create faster design...
- 5 Jun 2020

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