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Latest Blog Posts

  • Analog/Custom Design: Virtuosity: Smart View Multi-Process Corners in Virtuoso ADE Assembler and Explorer

    Arja H
    Arja H
    Click here to read the latest blog about the updated 'Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit'. This not only explains how to set up and simulate with a Smart View, but also discusses how to simulate with multi-process corners defined in the Smart View.
    • 17 Sep 2020
  • Breakfast Bytes: Cadence Triple Gold at the Stevie Awards

    Paul McLellan
    Paul McLellan
    Do you know what the Stevie Awards are? Officially, they are the International Business Awards, but just like the Academy Awards of Merit are colloquially known as Oscars, these awards are known as Stevies. They are: a set of eight business awards ...
    • 17 Sep 2020
  • Verification: JasperGold FPV: Asynchronous Designs? No Problem!

    XTeam
    XTeam

    Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low power dissipation, or even if you do have a system clock but it’s noisy, your design may be asynchronous, and that’s okay. It’s no secret that asynchronous designs are a challenge—so what…

    • 16 Sep 2020
  • Verification: Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping

    XTeam
    XTeam

    If you’re not familiar with the Arm/Cadence collaboration, you’ve been missing out. Arm has been using Cadence’s virtual system platform—Palladium® Z1 for emulation and Protium S1 for prototyping—for years, and with these, Arm powers their wide array of fast models for virtual prototyping to make the emulation process even faster than it already is. 

    Interested? 

    Well, it’s no secret that…

    • 16 Sep 2020
  • Breakfast Bytes: RISC-V State of the Universe

    Paul McLellan
    Paul McLellan
    A couple of weeks ago was the RISC-V Global Forum. This was truly global, in that it started at midnight California time and ran for 18 hours until 8:00pm the following evening, with people presenting from their living rooms all over the world. Prese...
    • 16 Sep 2020
  • Digital Design: Join Us for a Deep-Dive into Block Implementation with Innovus Using the Stylus Common User Interface

    Attila Zsigmond
    Attila Zsigmond

    If you are looking for a comprehensive training on block implementation with Innovus using the Stylus Common User Interface, look no further. This 3-day training, suitable for both beginner- and advanced designers, will take you through the complete digital block implementation flow, offering a detailed break-down of all implementation steps, while making you familiar with the graphical user interface, commands and attributes…

    • 15 Sep 2020
  • System, PCB, & Package Design : BoardSurfers: Installation Know-How: Which Installation Method is Right for You?

    Shikha Jain
    Shikha Jain
    Installing new software seems like a daunting task for most of us. You may feel burdened with concerns like how to install and what options to choose, and so on. So, in this post, I will unload your worries and share some best practices to make the i...
    • 15 Sep 2020
  • System, PCB, & Package Design : IC Packagers: Shrinking Dies Inside the Package Layout

    Tyler
    Tyler
    There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool. For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that do...
    • 15 Sep 2020
  • Breakfast Bytes: PSpice for TI

    Paul McLellan
    Paul McLellan
    Texas Instruments (TI) is the biggest analog semiconductor company in the world. As it happens, I wrote about TI just two weeks ago in my self-explanatorily-titled post Cadence Wins Texas Instruments' Supplier Excellence Award.  I gave...
    • 15 Sep 2020
  • カスタムIC/ミックスシグナル: Start Your Engines: ブログメーターの確認

    Custom IC Japan
    Custom IC Japan
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 ”ブログメ...
    • 14 Sep 2020
  • Breakfast Bytes: What to Do About IP Developed Before ISO 26262?

    Paul McLellan
    Paul McLellan
    If you have paid even passing attention to what has been going on in automotive functional safety, then you'll have heard of ISO 26262. You may even know that chapter 11 is the best! That's the one about semiconductors and semicondu...
    • 14 Sep 2020
  • Breakfast Bytes: Sunday Brunch Video for 13th September 2020

    Paul McLellan
    Paul McLellan
    https://youtu.be/aqlmfd3g5G0 Made in "Jaipur, India" Monday: Labor Day Tuesday: Andrew Kahng and Matthew Morrison on Industry and Academia Wednesday: OIP Ecosystem Forum 2020 Thursday: HOT CHIPS: The Space Race for the Biggest ML Machine Friday: Use ...
    • 13 Sep 2020
  • Verification: Celsius on Protium - Using Cadence Tools to Improve Cadence Tools?

    XTeam
    XTeam
    The Cadence tool flow is the most comprehensive flow around. If there is an EDA need, you can rest assured that Cadence has a tool that covers that need, and you can be certain that it integrates into the rest of the flow smoothly. In fact, Cadence t...
    • 11 Sep 2020
  • Digital Design: Library Characterization Tidbits: The Perfect Solution for Validating Libraries

    HelenShi
    HelenShi
    A library view contains electrical information that is used throughout design implementation starting from logic synthesis through design optimization to the final signoff verification.
    • 11 Sep 2020
  • Breakfast Bytes: Use Your Imagination to Get Smaller, Faster Chips

    Paul McLellan
    Paul McLellan
    At the recent CadenceLIVE Americas, Nick Loebner of Imagination Technologies presented Delivering Best PPA on PowerVR GPUs Using Genus/Innovus Digital Implementation System. You probably already know that Imagination Technologies license GPU IP....
    • 11 Sep 2020
  • カスタムIC/ミックスシグナル: Virtuoso Video Diary: 信頼性解析の改善

    Custom IC Japan
    Custom IC Japan
    IC6.1.8/ICADVM18.1 ISR3のVirtuoso® ADE Assembler および Virtuoso ADE Explorer で、信頼性解析の実行方法を完全に変更する、改良されたReliability Options フォームを導入しました。これまで以上に物事をより良くするために、ケイデンスは信頼性解析の改良を続けています。 このブログでは、すでに持っているものを再利用するという概念を中心とした2つの機能強化について説明します。 ストレス・ファイルの再利用 信頼性解...
    • 10 Sep 2020
  • Analog/Custom Design: Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE Explorer

    Arja H
    Arja H
    Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.
    • 10 Sep 2020
  • Breakfast Bytes: HOT CHIPS: The Space Race for the Biggest ML Machine

    Paul McLellan
    Paul McLellan
    At the recent HOT CHIPS, the Sunday morning tutorial was on scale out of deep learning training. I covered the introduction in my post HOT CHIPS: Scaling out Deep Learning Training. The second half of the morning was devoted to some of the biggest sc...
    • 10 Sep 2020
  • Verification: Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

    XTeam
    XTeam

    Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered. 

    Cadence has been partnered with Nvidia Mellanox for years, helping them build complete end-to-end solutions for everything from networking to data centers. Mellanox provides and handles every aspect of the process, and they’ve got a long track record of delivering breakthrough…

    • 9 Sep 2020
  • Breakfast Bytes: OIP Ecosystem Forum 2020

    Paul McLellan
    Paul McLellan
    Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosyst...
    • 9 Sep 2020
  • System, PCB, & Package Design : BoardSurfers: Find by Name or Find by Query - That is the Question!

    BarbS
    BarbS
    You must be using find utility day in and day out, but if you are unfamiliar with Find by Query in Allegro Layout Editors, read on. Layout editors retained the original Find by Name when developing a new utility to do what Find by Name cou...
    • 8 Sep 2020
  • System, PCB, & Package Design : IC Packagers: Preparing a Completed Package for Mounting on a PCB

    Tyler
    Tyler
    We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...
    • 8 Sep 2020
  • Breakfast Bytes: Andrew Kahng and Matthew Morrison on Industry and Academia

    Paul McLellan
    Paul McLellan
    I attended two presentations on the academic track at the recent CadenceLIVE Americas. The first was Andrew Kahng's presentation A 'Life Cycle' of Teaching and Research on EDA and IC Implementation Methodology. The second was Matthew...
    • 8 Sep 2020
  • 定制IC芯片设计 : Virtuoso Meets Maxwell: 当裸片版图没有Bump,有Pad Shapes时,怎么输出裸片版图?

    deeptig
    deeptig
    如果您的裸片版图不是通过Bumps,而是通过 pad shapes和标签来识别I / O位置,那么您可能会有种无所适从的感觉。 因此在这篇文章中,我将为大家介绍一种新的适用于裸片版图的解决方案。
    • 7 Sep 2020
  • Analog/Custom Design: Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability Between Best-In-Class IC and IC Packaging Design and Verification Tools

    danbaldwin
    danbaldwin
    Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s…
    • 7 Sep 2020
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