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Verification: Have You Ever Wanted to Learn Specman/e and Did Not Know How?

teamspecman

As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First, when you look for your next exciting verification position, the more HVL you know, the more options you have. In addition, you reflect yourself as a knowledgeable person for potential employers. Secondly, familiarity with several HVL, makes you a better verification…
- 11 Nov 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: チップにとらわれない – ICとICパッケージ設計および検証ツール間におけるクラス最高の相互運用性の優位点

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 10 Nov 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: RF PCB Design Flow Using Allegro Editors

Shreyansh

Allegro® RF PCB solution provides you with a unified design solution for complex mixed-signal projects. From schematic to layout and manufacturing, a total front-to-back design flow helps you streamline your entire RF design process. You lay RF ...
- 10 Nov 2020
Digital Design: Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges

timjedwards

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.
- 10 Nov 2020
System, PCB, & Package Design : IC Packagers: Key Functions for Good SKILL Programming in Allegro Package Designer

Tyler

Many of you out there are SKILL coders (or have these people on your team). SKILL is the extension programming language for all the backend layout products in the Allegro family, including Allegro Package Designer. If you’ve read up on the blog...
- 10 Nov 2020
Analog/Custom Design: Virtuosity: The Debut of the Virtuoso EMIR Analysis Flow for DSPF

Pallabi R

Do you want accurate extraction data for your design, regardless of foundry process and node? Do you want to complete your EMIR setup entirely within the Virtuoso framework? Then explore the new Virtuoso EMIR DSPF flow…
- 10 Nov 2020
Breakfast Bytes: SRC/SIA Decadal Plan for Semiconductors

Paul McLellan

The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) recently put out the Interim Report for the Decadal Plan for Semiconductors. The full report is planned for later in the year. To set some context, here is ...
- 10 Nov 2020
System, PCB, & Package Design : 2019 HF4 Release for Clarity, Celsius, and Sigrity Tools Now Available

SigrityReleaseTeam

The 2019 HF4 production release for Clarity, Celsius, and Sigrity tools is now available for download at Cadence Downloads.
- 9 Nov 2020
Life at Cadence: Computational Software: A New Paradigm for EDA Tools

Corporate

EDA tools have been evolving since the mid-1980s. The development can be broken down into three major phases, and it’s important to understand these three phases to realize where EDA tools are now, where the tools are much more tightly integra...
- 8 Nov 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso ADE Assembler と Explorer を使用したポストレイアウト容量の調査

Custom IC Japan

ポストレイアウトは最近注目の話題になっています。私と他の何人かのエンジニアは過去1年ほどの間これにより非常に忙しくなりました。私たちがVirtuoso® ADE AssemblerとVirtuoso® ADE Explorerに追加した新しくエキサイティングなポストレイアウト機能の一つがSpectre® Classic Simulatorのnetcapレポートを表示する機能です。この機能はIC6.1.8/ICADVM18.1ISR13から利用可能です。 Virtuoso ...
- 5 Nov 2020
Digital Design: Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 2

AbhaRawat

This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.
- 5 Nov 2020
Academic Network: System Design and Verification Training Deep Dive: Part 3

Kira Jones

As we continue the System Design and Verification Online Training deep dive, we’ll be covering C++ and SystemC languages. These courses should be taken after the recommended courses in Part 1 and Part 2, as the previous parts will provided help...
- 5 Nov 2020
Analog/Custom Design: Start Your Engines: The Blog-o-Meter Check - Lap 2

Jommy

This blog summaries the latest five blogs published in the Start Your Engines series.
- 5 Nov 2020
System, PCB, & Package Design : Implement SI and PI in High-Speed Memory Interfaces

Sigrity

Signal integrity (SI) engineers tasked with successfully implementing memory interfaces, such as DDR4 and DDR5, face major challenges in meeting the requirements in a timely fashion. The traditional design workflow typically assumes an ideal power d...
- 5 Nov 2020
Breakfast Bytes: TSMC, Microsoft, Cadence: Signoff in the Cloud

Paul McLellan

As you can guess from the title of this post, TSMC, Cadence, and Microsoft have been working together on signoff in the cloud. Since signoff comes later in the design cycle and is CPU intensive, it is an ideal part of the flow to make use of the clou...
- 5 Nov 2020
Analog/Custom Design: Virtuosity: Conserve Power— Setting up Virtuoso Power Manager

deeptig

This time I am back with a blog that briefly explains how to set up Virtuoso Power Manager before proceeding with low power verification. To run in-design checks, extract the power intent from a design, or run Conformal Low Power checks, you must first provide inputs that are required by the tool for correct identification of design topology and define the set of rules that apply to those design structures. For example…
- 4 Nov 2020
Breakfast Bytes: A Brief History of Cadence IP

Paul McLellan

I actually ran one of the earliest IP businesses, just not at Cadence. When we spun Compass Design Automation out of VLSI Technology, we had the library designers and the library product lines. So that was standard cells, memories, and gate arrays. V...
- 4 Nov 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Unified Libraries — クロスプラットフォームフローへの道を拓く

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 3 Nov 2020
Analog/Custom Design: Virtuosity: Design, Plan, and Analysis - The 3 Sides Of A Coin, Episode 1

colint

Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.
- 3 Nov 2020
System, PCB, & Package Design : BoardSurfers: Allegro In-Design Reflection Analysis: Signal Integrity Simulations on the PCB Canvas

Shirin Farrahi

Reflections happen on Printed Circuit Boards (PCBs) whenever signals encounter an impedance discontinuity, so maintaining constant impedance along all interconnects is always desirable. But it’s not always possible to achieve this. In order to ...
- 3 Nov 2020
System, PCB, & Package Design : IC Packagers: Allegro Package Designer and 3D DXF

Tyler

Hello, all. As we push towards the next major update to the 17.4 release, the team here at Cadence is very busy! We hope you’ll be as excited by the new updates, enhancements, and bug fixes as we are. But until then, there is still plenty of ca...
- 3 Nov 2020
Breakfast Bytes: Jumping Jack Flash

Paul McLellan

This is the second post about non-volatile memory technologies. The first post was EPROM: Chips with Windows. Today we move to flash memory. This was originally invented by Toshiba in 1980 as a derivative of the EEPROM technology discussed in the fir...
- 3 Nov 2020
Breakfast Bytes: Agricultural Electronics

Paul McLellan

In my post Jobs: Farmer I wrote about my experience as a teenager working on the farm owned (actually rented from the Duke of Badminton) by the father of one of my school friends. Electronics were nowhere to be found in those days. I recently watched...
- 2 Nov 2020
PCB、IC封装：设计与仿真分析: 如何在IC封装中连通晶片与球栅阵列封装（BGA）？

TeamAllegro

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年，专注于IC封装与中介层基板设计。同时，参与全Allegro平台、Virtuoso、PVS、OrbitIO及 Innovus产品的核心工作。 space BGA元件的主要作用是将其保护的裸晶（die）的信号经由BGA的焊球重新分配到其所安装的主机PCB上。因此，许多IC封装设计团队都不绘制前端原理图。即使有原...
- 30 Oct 2020
Breakfast Bytes: EPROM: Chips with Windows

Paul McLellan

I like to do the (London) Times crossword most days. For more information on how cryptic crosswords even work, see my offtopic post Aren't All Crosswords Cryptic? There's also a blog where each day the crosswords get analyzed and critiqued,...
- 30 Oct 2020

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