Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

System, PCB, & Package Design : CFD: It's More Than an Acronym - Learn More at CadenceLIVE

John Chawner

Excuse me, sir. Are you lost? That's what you might be thinking. Why is this guy - an aerospace engineer and CFD guy, a guy who's been with Cadence only six weeks, a guy who admittedly knows nothing about electricity except that it hurts whe...
- 1 Jun 2021
Breakfast Bytes: Countdown to TSMC Technology Symposium: 7nm, 5nm, 3nm, June 1

Paul McLellan

Today it is the TSMC 2021 Online North America Technology Symposium (tomorrow for China, Europe, Taiwan). Usually, I do a preview post about what is coming up and what is on the agenda, but last week was just too crowded with Cadence announcements (s...
- 1 Jun 2021
Analog/Custom Design: Virtuoso Meets Maxwell: Defining Ports in EMX Planar 3D Solver

kfullerton

Fast and accurate electromagnetic simulation is becoming critical in a growing number of applications, and defining ports correctly is one of the most important things to get right to ensure accuracy. In this blog I will share some insights on defining ports for the EMX Solver.
- 31 May 2021
PCB、IC封装：设计与仿真分析: 如何在IC封装设计中告别锐角问题？

TeamAllegro

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年，专注于IC封装与中介层基板设计。同时，参与全Allegro平台、Virtuoso、PVS、OrbitIO及 Innovus产品的核心工作。锐角，无论是在浇注的铺铜中产生尖锐棱角，还是在两块不同的金属之间形成锐角，都是一个棘手的问题。作为设计师，我们会不遗余力地尝试避免上述情况；但是尽管付出诸多努力，锐角还是...
- 28 May 2021
Digital Design: Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

Vijetha

In the concluding blog of our "Demystifying ESD" series, we walk you through the features of the Voltus Electrostatic Discharge (ESD) analysis reports that provide a clear insight on your design's vulnerability to ESD, from the early-design phase to tapeout.
- 28 May 2021
Digital Design: SSV 21.1 Base Release Now Available

SSV Release Team

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 21.1 release, see the README.txt file in the installation hierarchy. SSV211 Here is a ...
- 28 May 2021
Breakfast Bytes: Offtopic: "Pole Pole" to the Top of Kilimanjaro

Paul McLellan

Today is the last blogging day before Memorial Day on Monday, so as is now traditional, I go off-topic. Today, high points of my life. As in high points in the world that I have been to. The highest point in the UK is Ben Nevis in Scotland, at 4,413&...
- 28 May 2021
Computational Fluid Dynamics: Fluid Dynamics Investigation of the Sonic Boom on a Supersonic Aircraft

AnneMarie CFD

The return to supersonic flight is amongst the hottest topics in aviation today, as several companies (Boom Supersonic and Aerion, among others) are actively developing new supersonic commercial airliners targeted to enter in service in the comi...
- 27 May 2021
Breakfast Bytes: Why Attend CadenceLIVE Americas 2021 on June 8 and 9?

Paul McLellan

Once again this year, CadenceLIVE Americas is coming up soon and it will be completely virtual. As I do each year, let me give you some good reasons to attend. We'd love to give you food and drink but you know why that is not going to happen. We stil...
- 27 May 2021
Analog/Custom Design: Virtuosity: Learn the Right Steps—Design 5G Your Way with Cadence Training

Parula

In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz. We are also happy to announce and introduce our brand new corresponding training on June 14th 2021.
- 27 May 2021
定制IC芯片设计 : Virtuoso Video Diary: “Training Bytes” 助推知识传播—第5部分

Parula

2021年Knowledge Booster 系列博客，我们将介绍如何修改相关参数来解决Spectre Simulation DC的收敛问题和报错问题。
- 27 May 2021
Analog/Custom Design: Spectre Tech Tips: Introducing Spectre Analog Fault Analysis

Jianhe Guo

Chip tests have become more demanding as defects tend to occur more often in scaled down processes. In this blog, we'll discuss how you can use the Spectre Fault Analysis to improve test coverage by identifying critical test patterns.
- 26 May 2021
Breakfast Bytes: Bringing Clarity to the Cloud

Paul McLellan

Cadence announced Clarity 3D Solver Cloud as part of Cadence Hybrid Cloud, providing cloud-based system analysis as the click of a button.
- 26 May 2021
System, PCB, & Package Design : IC Packagers: Analyzing and Fixing Wire Bond-Specific Design Issues

avijeet

Design reuse is the key to faster design cycles in today’s packaging design industry, where the shortest possible time to market makes or breaks the success of a product. As most of the package designs have wire bonding, sharing the wire bondin...
- 26 May 2021
Computational Fluid Dynamics: Tutorial Tuesday - It's Time to Learn Some Meshing

John Chawner

Today's not just Tuesday, it's Tutorial Tuesday. What's that, you ask? Each Tuesday for what seems like forever, we've been publishing a new video on Pointwise's YouTube channel. And these aren't just any videos. They help you...
- 25 May 2021
Breakfast Bytes: Rapid Adoption Kits for Arm's Premium Mobile Platforms

Paul McLellan

Today, Arm announced its new lineup of processors for mobile. These are the first Arm v9 instruction set (ISA) CPUs, new Mali GPUs, and new system interconnect. Cadence announced rapid adoption kits for the premium platform, which consists of th...
- 25 May 2021
System, PCB, & Package Design : BoardSurfers: Managing Minor Spacing DRCs Using Manufacturing Tolerances

Boopathy J

While translating boards from different PCB design applications or changing design units in the later phase of a design cycle, a wide variety of mathematical round-offs may occur for geometric computations. As DRCs are logically computed, the DRCs cr...
- 25 May 2021
SoC and IP: Introducing Cadence IP for PCIe 6.0

tonychen6636

Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous in the modern digital world. Today, PCIe is an indispensable technology found in high-performance computing, AI/ML accelerators, network adapters, and solid-state storage, to name a few. In addition, recent advances in speed and latency of PCIe have allowed it to gain wider adoption within the memory hierarchy as well (e.g., persistent…
- 24 May 2021
Breakfast Bytes: PCIe 5.0 and 112G-LR IP in TSMC N5

Paul McLellan

Well, that's a lot of tech gobbledegook in the title of this post. Here's what it means. This morning Cadence announced that its IP interfaces for low-power PCI Express (PCIe) 5.0 and for 112G long reach (112G-LR) are available on TSMC's ...
- 24 May 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

This week’s CFD news includes both an image of the week and an application of the week – draw your own conclusions. We’re still seeing a lot of online events but I am happy that AIAA SciTech 2022 looks to be an online and in-person ...
- 21 May 2021
Breakfast Bytes: Linley: Habana and Cerebras

Paul McLellan

In the recent Linley Spring Processor Conference, there were many processors for various kinds of AI, deep learning, and inference. As I said in my overview post Linley: Driving AI from the Cloud to the Edge, I don't think that all these products...
- 21 May 2021
カスタムIC／ミックスシグナル: Spectre FX: FはFastのF、本当に高速

Custom IC Japan

本日5月20日(米国時間)、ケイデンスは、最大で3倍の速度（同等以上の精度で）を持つ次世代FastSPICE回路シミュレータSpectre FX Simulatorを発表しました。このシミュレータは、メモリを含む複雑なアナログおよびカスタムデジタルブロックとサブシステムの大規模なシミュレーション検証の課題を解決します。 Spectre FXについて聞いたとき、まず「待てよ、私は20年前にCustom ICを担当していた時にFastSPICE製品があったはずだが」と思いました。Spectre F...
- 20 May 2021
Spotlight Taiwan: 增強系統分析與PCB設計研發戰力 - 隨選影片向您致敬!

candyyu

PCB設計暨系統分析 - 強檔精彩影片回顧! 5G、AI、工業物聯網（IIoT）、自駕車和超大規模（hyperscale）運算等技術的匯聚，為半導體產業帶來了新商機，但同時也推升了系統設計的複雜度。隨著異質整合技術的快速進展，現在，我們正處於電子設計演進的轉捩點，需要突破傳統的新思維與做法。因此，為了滿足電子設計朝更高整合度和多樣化垂直應用發展的趨勢，業界需採用「超越晶片」的全流程設計，才能夠快速、準確、全面性地克服日益嚴苛的系統級分析與設計挑戰。Cadence已建構了全流程解決方案...
- 20 May 2021
Breakfast Bytes: Spectre FX: F Is for Fast, Really Fast

Paul McLellan

Today, Cadence announced the Spectre FX Simulator, a next-generation FastSPICE circuit simulator with up to 3X the performance of anything else in the market (at the same accuracy or better). It solves large-scale verification simulation ch...
- 20 May 2021
Life at Cadence: Moore’s Law Is Still Accelerating

Chin-Chi Teng

Moore’s Law Is Still Accelerating. I’m looking at Moore’s Law differently, measuring the pace of new node arrivals. Cadence is at the forefront of the transition to 3nm, actively working with early adopter customers
- 19 May 2021

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.