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Breakfast Bytes: Presidents' Day Off-Topic: Why You Can't Say "Red Little Riding Hood"

Paul McLellan

Monday is Presidents' Day, and Cadence (in the US) will be off for the day. Breakfast Bytes will be off, too, and as is now traditional, the post before the break is about whatever I feel like. Today, some obscurities about English that you probably ...
- 15 Feb 2019
Computational Fluid Dynamics: ENTECHMACH: Multidisciplinary Design Optimization of a Multi-Stage Centrifugal Compressor

AnneMarie CFD

Authors: Vladimir Neverov, Ivan Cheglakov, Specialists on compressor machines, Aleksandr Liubimov, Head of Advanced Development and Design Department, ENTECHMACH, Russia. Research-and-production Company «ENTECHMACH», located in Saint Pe...
- 15 Feb 2019
Analog/Custom Design: Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts electrically correct

NamrataM

Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster…
- 14 Feb 2019
Breakfast Bytes: Embedded in Nuremberg

Paul McLellan

The last week of February is Embedded World (or, in fact, embeddedworld since they fashionably use all lower case). It is 26th to 28th February in the Exhibition Center. It is the same week as MWC Barcelona, DVCon (San Jose), and SPIE Advanced Lithog...
- 14 Feb 2019
Breakfast Bytes: MWC Barcelona: 5G in Catalonia

Paul McLellan

The last week of February is MWC Barcelona, formerly known as Mobile World Congress but now officially just initials. It is, obviously, in Barcelona, Spain. If you are in Germany, or Silicon Valley, other conferences are available! That week is ...
- 13 Feb 2019
Breakfast Bytes: DVCon Preview: The Year of PSS

Paul McLellan

The biggest conference on verification is DVCon, which takes place in the San Jose Doubletree Hotel from 25th to the 28th February (yes, the same week as SPIE...and Embedded World...and Mobile World Congress). Verification covers all of simulation, e...
- 12 Feb 2019
Breakfast Bytes: SPIE 2019: Light Entertainment

Paul McLellan

SPIE is the international society for optics and photonics, with the purpose of “advancing an interdisciplinary approach to the science and application of light”. What everyone calls "spie" (pronounced "spy"), however,...
- 11 Feb 2019
Breakfast Bytes: Sunday Brunch Video for 10th February 2019

Paul McLellan

https://youtu.be/evsNzak23b4 Made at Cadence basketball court (camera Sean) Monday: DesignCon: Cadence Teaches AMI and IBIS Tuesday: Emerging Memories Poised to Explode Wednesday: DesignCon 2019 Thursday: 60 Years of DARPA—61 Actually...
- 10 Feb 2019
PCB、IC封装：设计与仿真分析: 机械、热、SI、PI 、EMI分析：PCB设计缺一不可

SDA China

本文翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章 "Mechanical, Thermal, EMI, SI, PI: PCB Design Needs Them All" 。 space An-Yu Kuo博士曾经在Cadence CDNLive以色列分会场的开幕演讲上讨论过 “PCB设计与分析中弥合电气、机械等领域之间的差距” 主题。现如今，PCB设计与分析涵盖更多领域：电磁学的多物理分析、信号完整性分析、传热分析、...
- 8 Feb 2019
Breakfast Bytes: Will Crypto Change the World?

Paul McLellan

Do you remember when you had to pay for ringtones? In 2005, analysts were predicting that ringtones would be a $10+B market by 2010. In that pre-smartphone era, you could only install a ringtone if your service provider gave you permission. You had t...
- 8 Feb 2019
Analog/Custom Design: Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET Design

Hiro Ishikawa

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.
- 7 Feb 2019
System, PCB, & Package Design : Simulation for a Song: Downloading Models from the Web and Associating with Parts for PSpice Simulation

mrigashira

While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode or Sweet Home Alabama (even though I don’t live in Alabama), the music being an active part of the journey, especially when I am just beginning the drive, fresh and eager, looking forward to the trekking and wildlife sightings. Compare this with the schematic design phase. Whistling and nodding while placing the parts: here’s the…
- 7 Feb 2019
Analog/Custom Design: Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!

Rashmi G

Cutting-edge innovation…Top-down planning…Reliable and formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso^® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and…
- 7 Feb 2019
Breakfast Bytes: 60 Years of DARPA—61 Actually

Paul McLellan

On 4th August 1957, the Soviet Union launched the first artificial satellite, Sputnik 1 ("sputnik" means "satellite" in Russian). It wasn't very impressive by modern standards, a 23" metal sphere with 4 radio antennas. It seems that President Eisenho...
- 7 Feb 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

Virtuoso Release Team

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download.
- 6 Feb 2019
Breakfast Bytes: DesignCon 2019

Paul McLellan

It doesn't seem to matter what a show is ostensibly about at the moment. Every show seems to be talk about quantum computing, 5G, or artificial intelligence (AI). DesignCon, the focus of which is PCB design, was no exception, with three keynotes on.....
- 6 Feb 2019
定制IC芯片设计 : Virtuosity: 如何使用ADE Explorer 及ADE Assembler 打开旧版本的ADE 状态和视图文件

NamrataM

您是否发现，当您查看 Virtuoso ® ADE L 状态（State）文件，或者 Virtuoso ® ADE XL 视图 (View) 文件时，默认打开程序仍然是旧版本的 ADE L 或者XL? 如果您已经移动至 Virtuoso ® ADE Assembler 或者 Virtuoso ® ADE Explorer，那么需要打开文件，在 Open File 对话框下，找到应用程序这栏，并将其更改为...
- 5 Feb 2019
Breakfast Bytes: Emerging Memories Poised to Explode

Paul McLellan

A couple of weeks ago was the Persistent Memory Summit. (For more details, see my post Persistent Memory.) Normally, this might be a minority-interest event, but the potential arrival of a new level in the memory/storage hierarchy means that everyone...
- 5 Feb 2019
Breakfast Bytes: DesignCon: Cadence Teaches AMI and IBIS

Paul McLellan

At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced IBIS-AMI Techniques for 32 GT/s and Beyond. If you are not well-versed in SerDes and signal integrity, your first need for a tutorial might be to explai...
- 4 Feb 2019
PCB、IC封装：设计与仿真分析: 2019七大行业动向预测

SDA China

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “Breakfast Nibbles: Predictions for 2019"。新年伊始，我来和大家聊聊我眼中的2019年业内主题趋势。内存价格 2018年，整个半导体市场非常强劲，其中很大一部分原因是内存市场尤其是DRAM市场的需求远大于现有产能。而随着额外产能的上线，关注内存市场的人无一不认为其价格将会发生下滑（更多详细内容，请阅读 "Semicon...
- 3 Feb 2019
Breakfast Bytes: Sunday Brunch Video for 3rd February 2019

Paul McLellan

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM: Embedded Memories Tuesday: CES: 5G, All Hat and No Cattle Wednesday: Persistent Memory Thursday: What Next for Modus DFT? Friday: Programming Persistent Memory www.b...
- 3 Feb 2019
Breakfast Bytes: Programming Persistent Memory

Paul McLellan

I talked earlier this week about the recent persistent memory summit (see my post Persistent Memory). If DRAM gets faster or higher capacity, then there isn't anything that software engineers need to change, whether they're writing the operating syst...
- 1 Feb 2019
Analog/Custom Design: Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

Yagya Mishra

An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This…
- 31 Jan 2019
Breakfast Bytes: Persistent Memory

Paul McLellan

Last week was the latest Persistent Memory Summit. In the semiconductor world, we don't usually use that word, we say non-volatile memory. In practice, this mostly means flash memory (mainly 3D NAND today) and embedded flash memory (eFlash). Both...
- 30 Jan 2019
Breakfast Bytes: What Next for Modus DFT?

Paul McLellan

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the same glory as the more high profile parts of the EDA flow such as synthesis, or place & route, or signoff. Test History Over the years, how we do test has...
- 30 Jan 2019

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