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Spotlight Taiwan: 類比與混合訊號系列線上精選影片，帶領您征服設計挑戰!

candyyu

Cadence類比與混合訊號系列線上活動已圓滿落幕，在此為您準備精彩視頻重播，集結四場Cadence技術專家開講，深入解析與探討引領業界的類比與混合訊號技術產品，協助您的設計更精進、提升生產力！本系列影片由Cadence 類比與混合訊號專家團隊演說，不論您是否錯過先前線上研討會，亦或想重溫演講內容，只要簡單註冊Cadence.com 成為線上會員，所有豐富訊息即可信手拈來! 1. 主題: 高效類比IC設計與驗證良方 &n...
- 16 Sep 2021
The India Circuit: The most awaited... CadenceLIVE India 2021: Best Presentation Awards

sangramjena

CadenceLIVE, Cadence’s annual user conference, has been a great platform for Cadence technology users, developers, and industry experts to connect, share ideas and best practices solve design challenges, and inspire design creativity. This...
- 16 Sep 2021
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 9 Introduction to Virtuoso Module Generator and Virtuoso Floorplanner

Parula

This Blog shows how the Virtuoso Module Generators provide a way to generate multiple Pcell instances into a complex, highly matched, structured array and how you can control the routing style and generate internal routing geometry. In addition, you get an insight into Floorplanner that consists of automatic and interactive floorplanning tools and technologies that help the mixed-signal designers to develop a layout from…
- 16 Sep 2021
Breakfast Bytes: HOT CHIPS: Two Big Beasts

Paul McLellan

Today, I'm covering two of the biggest chips presented at the recent HOT CHIPS. Ponte Vecchio, Intel's enormous graphics chip intended to be used in Argonne National Laboratories' supercomputer Aurora. And the latest developments from Cer...
- 16 Sep 2021
Breakfast Bytes: Pegasus Flies into the GF Technology Summit

Paul McLellan

Today is the GF Technology Summit, what used to be called GTC in previous years. GF is, of course, GlobalFoundries. We also announced this morning that the Pegasus Verification System has been certified by GF on its 12LP, 12LP+, and 22FDX processes. ...
- 15 Sep 2021
RF /マイクロ波設計: 新しい通信システム解析向けソリューション: Rohde＆Schwarz社の標準規格信号を設計で活用

RF Design Japan

本記事は2021年8月のMicrowave Product Digestに投稿した記事を翻訳したものです。 RF系および部品の設計からCadence VSSおよびRohde＆Schwarz VSESIM-VSSソフトウェアを使用した実装まで by Dr.Gent Paparisto and David Vye, Cadence and Markus Loerner, Rohde & Schwarz 　　電子設計自動化（EDA）ソフトウェアを使用した解析は、...
- 14 Sep 2021
System, PCB, & Package Design : (P)SpiceITUp: Managing the Stress Levels of Design Components

mrigashira

I came across a question on a social media site about how to know when the absolute maximum ratings for a component have been exceeded? In other words, how do you identify components that are stressed due to power dissipation, increase in junction te...
- 14 Sep 2021
Spotlight Taiwan: 2021 CadenceLIVE Taiwan 使用者大會 - 10月7日隆重登場!!

candyyu

今年可說是半導體產業重要的一年，因為電子產品供需失衡、晶片短缺的情況，讓我們更體認到肩負半導體晶片開發的工作，對全世界來說有多麼重要，而如何協助全球經濟向前邁進，也是我們身為半導體產業一份子的使命! 每年由Cadence所舉辦的CadenceLIVE使用者大會是一年一度的半導體盛會，集結Cadence合作夥伴、業界專家、技術用戶及開發人員，精采呈現技術趨勢與創新應用演講。今年即將在10月7日(四) 線上舉辦，只需要您立即點選下方報名連結並準時參加，您將成為半導體科技競逐一員，見證風起...
- 14 Sep 2021
Life at Cadence: AI Everywhere and for Everyone!

Sanjive Agarwala

Cadence helps deploy Energy Efficient, Intelligent Devices over the Edge The AI landscape is evolving and has become a regular part of advanced technology. According to Omdia, the AI market will have a compound annual growth rate of 37%, reaching $5...
- 14 Sep 2021
Breakfast Bytes: How to Build a Data Center: It's All About the SerDes...and Thermal

Paul McLellan

Okay, you are probably not going to have to build a data center. But you might well be involved in designing chips that go in data centers. Or looking at IP for data centers. Or worrying about some aspect of design tools for advanced nodes, much of w...
- 14 Sep 2021
Computational Fluid Dynamics: I'm Marc Tombroff and This Is How I Mesh

John Chawner

You may be thinking, "He's not Marc Tombroff" and "What's this how I mesh?" First, Marc Tombroff is my new friend and colleague here at Cadence. He was the GM at Numeca prior to their acquisition by Cadence and he and I no...
- 13 Sep 2021
Breakfast Bytes: On-Device Artificial Intelligence the Tensilica Way

Paul McLellan

This morning, at a workshop at the AI Hardware Summit, Cadence is laying out details of its AI strategy and a new way that the product line of Tensilica processors will be structured going forward. On Wednesday morning, Sanjive Agarwal...
- 13 Sep 2021
Breakfast Bytes: Sunday Brunch Video for 12th September 2021

Paul McLellan

https://youtu.be/7gCLOVo1XQQ Made at Tesla Factory, Fremont (camera Ziyue Zhang) Monday: Labor Day Tuesday: HOT CHIPS: The Next-Generation of General-Purpose Compute Wednesday: NOT CHIPS: Tesla's Project Dojo Thursday: New Cerebrus...
- 12 Sep 2021
Breakfast Bytes: Cadence in Brazil

Paul McLellan

How much do you know about Brazil? Probably, like me, not that much. And most of that has to do with football. Or Caipirinhas. One thing that I know that a lot of people apparently do not is that the local language is not Spanish but Portuguese. In f...
- 10 Sep 2021
Computational Fluid Dynamics: What Our Interns Did This Summer on Cadence's Pointwise Meshing Team

John Chawner

There's just one problem with summer interns. As soon as you get to know them, they have to return to school. This loss is not diminished by the fact that ours (and probably yours too) had to work remotely this summer. (Which is still better than...
- 9 Sep 2021
Breakfast Bytes: New Cerebrus Webinar This Month

Paul McLellan

Cerebrus is Cadence's new machine learning-enabled digital design environment. When we announced the product in July, I covered it in my post Cerebrus: The Future of Intelligent Chip Design. Coming up on September 16 at 10:00am PDT is a new webin...
- 9 Sep 2021
Computational Fluid Dynamics: Upcoming NASA Seminar on Adaptive Meshing

John Chawner

Tomorrow morning, Cadence's Travis Carrigan and Nick Wyman will be participating in NASA's Advanced Modeling and Simulation (AMS) Seminar series when they share some of our latest progress in adaptive mesh generation. Here are the details of ...
- 8 Sep 2021
Breakfast Bytes: NOT CHIPS: Tesla's Project Dojo

Paul McLellan

Nope, NOT CHIPS is not a misprint. Tesla didn't present at HOT CHIPS. But they did have an AI Day just a couple of days later. What their team presented was pretty mind-blowing. There was a lot of stuff about self-driving software, training, and ...
- 8 Sep 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Export Die GUIが機能強化されさらに便利になりました

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 7 Sep 2021
Computational Fluid Dynamics: It's a Wrap! Cadence CFD at Aerovehicles-4 and AutoCFD-2

John Chawner

That’s a wrap! One week and two different CFD events in the automotive world and Cadence participated and presented at both. AutoCFD-2 This year's AutoCFD event (aka 2nd Automotive CFD Prediction Workshop) was rich in results and analyses f...
- 7 Sep 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

It's Friday, the weekend is upon us, and it's time for This Week in CFD. I am particularly grateful because today is one of Cadence's Global Recharge Days on which we can take a little R&R and step back from the work-from-home grind. ...
- 7 Sep 2021
Breakfast Bytes: HOT CHIPS: The Next-Generation of General-Purpose Compute

Paul McLellan

At the recent HOT CHIPS, the first day opened with the chips that you first think of when you hear the word processor. These are the next generation of chips from the likes of Intel, AMD, and IBM. There were lots of other chips too, such as Arm's Neo...
- 7 Sep 2021
PCB設計／ICパッケージ設計: IC Packagers: 新リリースには新しいものがたくさん！

SPB Japan

第3回目となる今回のブログでは、メジャーアップデートでの最大の新機能をご紹介します。本連載の第1回と第2回では、パフォーマンスの向上からグラフィックキャンバスの改善まで、さまざまな機能をご紹介しました。基本製品のアップデートや、オプションノード Silicon Layout の上級者向けアイテムなど、様々なアイテムをご用意しています。今回のAllegro® Package Designer Plus のアップデートでは、配線と電源供給ソリューションに加え、GDS製造出力に高度な特定のマ...
- 6 Sep 2021
PCB設計／ICパッケージ設計: IC Packagers: 新しいリリースについて他に知っておくべきことは？

SPB Japan

先週は、主に製造工程を対象とした新機能をご紹介しました。レイヤベースのデガス処理の改善、鋭角補正、そしてオリジナルのデザインに対して意図した製造マスクのレイアウト対レイアウト比較を行うツールなどです。ここで、別のクラスの改善点を見てみましょう: それは、デザインへの視覚的なアクセスを改善しながら、時間を節約できるものです。キャンバス上でのデザインの見え方や移動の速さから、既存のデザインで使用していた正常なメモリーダイスタックを新しいデザインに再利用することまで、皆さんがワクワクするようなアイ...
- 6 Sep 2021
PCB設計／ICパッケージ設計: IC Packagers: 17.4-2019 Hotfix 019 リリース！その意味とは？

SPB Japan

17.4-2019リリースのHotFix 019のダウンロードとインストールが可能になりました。今回のリリースは、3回目のメジャーアップデートとなり、多数のバグフィックス、エンハンスメント、新機能が追加されています。私はついに、それらについて皆さんとお話しできることに興奮しています。それでは、Allegro® Package Designer Plusでのパッケージデザイン体験を向上させる最大のアイテムをご紹介します。レイヤーベースのデガッシング（脱ガス）今回のアップデートの中で、私...
- 6 Sep 2021

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