Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Digital Design: Need Help with Liberate Commands and Parameters?

Jommy

Alexa, what is square root of 12547858?

Within some nanoseconds, Alexa gives you the answer to it. That's how convenient technology has made things for us! How cool would it be if Alexa could get some help with the usage of parameters or commands while scripting?

Well, we don't have Alexa to your rescue yet, but do have a cool help functionality that could save you time and effort of pulling out a reference manual…
- 3 Jun 2019
Breakfast Bytes: Spectre X: Same Accuracy, New Speed

Paul McLellan

This morning at DAC, Cadence announced the Spectre X Simulator, the latest version of its circuit simulation product. The short value proposition is up to 10X speed improvement, up to 5X capacity improvement, the same golden accuracy. So the same res...
- 3 Jun 2019
Breakfast Bytes: Sunday Brunch Video for 2nd June 2019

Paul McLellan

https://youtu.be/T2VZUEW1ucc Made at Protium Hardware Lab (camera Sean) Monday: Memorial Day Tuesday: Protium X1: FPGA Prototyping for the Enterprise Wednesday: Verific, 20 Years Terrific Thursday: Embedded Vision: Seeing Round Corners, and...
- 2 Jun 2019
PCB、IC封装：设计与仿真分析: SI工程师如何分析多千兆位串行链路、内存及接口

Sigrity

作者：Ken Willis 早在2007年，Cadence推动了对IBIS标准的扩展，即算法模型接口（AMI），可以模拟多千兆位串行链路接口。这与通道（与传统电路相对）仿真密切相关，可以模拟大量位比特流量仿真。当时的数据速率通常在2.5到5Gbps的范围内——即现在DDR4和DDR5的速率范围。有几件事情推动了对串行链路中通道仿真和AMI的最初需求。一个是在特定误码率（BER）下分析眼图与眼图模板（即波形禁止区域）的要求。根据经验模拟确定误码率是不切实际的（模拟1e16...
- 31 May 2019
Life at Cadence: Appreciating Our Employees

Mihaylov

Recognizing the Outstanding Effort that Makes Cadence Successful Cadence hires the best and brightest in our industry to help us elevate the team and solve technology’s toughest challenges for our customers. Our employees make a global impact a...
- 31 May 2019
Breakfast Bytes: ESD Alliance CEO Outlook: The Leading Edge, Chiplets, Design Costs, Security, and More

Paul McLellan

The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel one evening every spring. Originally, it was focused on the CEOs of the big EDA companies giving an outlook, but since one of them was always in its quiet period, and t...
- 31 May 2019
Verification: Got IP Security Questions? This Luncheon at DAC Has Answers

XTeam

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you’re planning to attend DAC, be sure to stop by the Accellera-sponsored Luncheon Focusing on IP Security Assurance Issues Led by Panel of Industry Experts. There, you’ll hear a short update on what Accellera’s been up to by Accellera Chair Lu Dai, and then the experts will jump right into a panel discussion covering all sorts of IP security…
- 30 May 2019
Breakfast Bytes: Embedded Vision: Seeing Round Corners, and Reasoning on Microcontrollers

Paul McLellan

May is a month that seems to have many things associated with it. "Sell in May and go away," people who work in the financial sector will tell you. Or "I thought that spring must last forevermore; For I was young and loved, and it was ...
- 30 May 2019
Verification: DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More

fschirrmeister

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...
- 29 May 2019
Analog/Custom Design: Spectre Tech Tips: Spectre APS Save Overview - Part 1

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated…
- 29 May 2019
Breakfast Bytes: Verific, 20 Years Terrific

Paul McLellan

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL. Verific got started twenty years ago, Rob De...
- 29 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM) – Part 1

References4U

In this week’s Whiteboard Wednesdays video, Amol Borkar explains how SLAM works. From the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Then he talks about the importance and the applications of SLAM. Finally, Amol talks about the building blocks of a SLAM flow. Must watch!

www.youtube.com/watch
- 28 May 2019
Verification: Thinci Finds Success with the Cadence Verification Suite

XTeam

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete Cadence Verification Suite to speed up the verification of their machine-learning and AI designs. Now, Thinci can access the new technologies available through the Cadence Verification Suite to shorten their product development time by months while improving verification coverage.

“We selected the Cadence Verification Suite because it enables…
- 28 May 2019
The India Circuit: Is The Gig Economy Is Here To Stay?

Madhavi Rao

While the term "gig economy" has been around a long time, it has gained traction in India only since around 2014 when Indian gig economy companies that hire a part-time workforce, such as Swiggy and Zomato (food delivery), Dunzo (delivery s...
- 28 May 2019
Breakfast Bytes: Protium X1: FPGA Prototyping for the Enterprise

Paul McLellan

Today Cadence announced the new Protium X1 Enterprise Prototyping Platform. The previous version, the Protium S1 Desktop Prototyping Platform, was the size of a small refrigerator and intended to be beside an engineer's desk. The Protium X1 platform,...
- 28 May 2019
System, PCB, & Package Design : IC Packagers: When Being Two-Sided is a Good Thing

Tyler

With each new generation, demand for smaller, faster, lighter, more efficient is at the top of the requirements list for most things. But, we cannot make things smaller forever. Instead, we need to look for more creative solutions. Where can we ...
- 28 May 2019
Breakfast Bytes: Sunday Brunch Video for 26th May 2019

Paul McLellan

https://youtu.be/mx1i55BxSTU Made at Cadence campus (camera Sean) Monday: Alberto and the Origins of the EDA Industry Tuesday: Samsung's 3nm GAA Process Wednesday: I/O Is Faster Than the CPU—What Now? Thursday: GOMAC: Software Is...
- 26 May 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: Minimum Screen Resolutions and Large Forms

Tyler

The Cadence® Allegro® backend layout tools are large, complex, highly-capable environments that provide you with a massive amount of functionality. Whether you are designing a rigid-flex PCB, a BGA package, an interposer, or something else entirely, they provide the features you need to accomplish the task.

However, with great functionality comes great… big forms, at times. Some of the largest forms in Allegro…
- 25 May 2019
PCB、IC封装：设计与仿真分析: 邀请函：2019 Cadence中国技术巡回研讨会

SDA China

诚邀您参加 “ 2019年度Cadence中国技术巡回研讨会”，会议将集聚Cadence的技术用户、开发者与Cadence资深技术专家，涵盖最完整的先进技术交流平台，从SoC设计、验证仿真到封装和板级设计的全流程的技术分享，您将有机会和开发Cadence工具的技术专家们面对面的直接沟通。 6月伊始，Cadence与您相约西安、成都、上海、深圳、北京！ space 会议为免费参加，座位有限，报名从速！会议咨询： event_cn@cadence.com 扫描下列二维码...
- 24 May 2019
Breakfast Bytes: Off-Topic: Syllepsis and Zeugma

Paul McLellan

It's Memorial Day in the US on Monday, and Cadence is off. So today is the day before a holiday. By tradition, I write about...whatever I feel like. So let's go with figures of speech. Even before I became a professional writer, I had a fasci...
- 24 May 2019
System, PCB, & Package Design : How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

Sigrity

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 di...
- 23 May 2019
Breakfast Bytes: GOMAC: Software Is Never Done

Paul McLellan

When I was at GOMAC in Albuquerque at the end of March, I ran into a couple of Cadence people and a couple of Green Hills people. Everyone left except one of the Green Hills guys, since he was staying in a different hotel. He turned out to be John Wa...
- 23 May 2019
Breakfast Bytes: I/O Is Faster than the CPU—What Now?

Paul McLellan

At his keynote at CDNLive Silicon Valley, Andy Bechtolsheim made a throwaway remark that 1600G Ethernet would be a problem since "the packet rate is just 333 picoseconds so that needs wide Ethernet ports" (see my post Andy Bechtolsheim...
- 22 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - The 4 Steps Necessary for an Effective Cloud-Based Design Strategy

References4U

In this week's Whiteboard Wednesdays video, Craig Johnson identifies the 4 steps to follow to create an effective strategy for moving electronic design work to the cloud. Skip one of these and your results could be disappointing.

https://youtu.be/rKoatyYa35E
- 21 May 2019
Analog/Custom Design: Virtuoso Video Diary: Comparing Multiple Tests and Sharing Settings

Yuan Li

Have you been in the situation where you want to change a particular simulation setting in several of your tests in Virtuoso ADE Assembler? This can be a tedious process as you have to figure out which tests have that setting and what it is set to, then you have to go in to each test in turn to change it. From IC6.1.8 ISR3/ICADVM18.1 ISR3, we have added a tool to do just that. You can compare all the simulator settings…
- 21 May 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.