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Breakfast Bytes: Cadence Cloud: The Video Version

Paul McLellan

Recently, Cadence released a series of videos about all the various aspects of Cadence Cloud. I'll start by summarizing them here, but mostly I'll just let the videos speak for themselves. I've written about Cadence Cloud quite a bit, so if you prefe...
- 13 Nov 2020
カスタムIC／ミックスシグナル: Virtuosity:Cadence Learning and Supportポータルの最新情報 – パート 1

Custom IC Japan

この数か月間の状況において、私たちは皆、新しい活動に熱中し、新しいことを学び、日常生活に何か興味のあることを加えています。似たような路線で、Cadence Learning and SupportポータルのCustom IC Design Flow/Methodology RAKシリーズを紹介します。 Custom IC Design Flow/Methodology RAKシリーズはサンプルデザインフローを案内し、いろいろな設計段階でのCustom IC Virtuoso Platformツ...
- 12 Nov 2020
Analog/Custom Design: Virtuosity: Conserve Power— Running In-Design Checks

Manishj

Today’s blog focuses on in-design checks that offer an easy and convenient way to identify common design issues encountered by the design community while implementing low power schemes. It also helps designers to uncover issues early in the design cycle, avoiding an ECO.
- 12 Nov 2020
Breakfast Bytes: Formal Verification Signoff for Digital IP

Paul McLellan

At the recent Jasper User Group meeting, one of the presentations was by David Vincenzoni of STMicroelectronics titled Formal Verification Signoff for Digital IP: Can We Use It? At the risk of revealing the answer to the question prematurely, it turn...
- 12 Nov 2020
Verification: Training Insights - Still Relying on Static-Only CDC Signoff? Introducing the JasperGold CDC App!

Nizar Hanna

RTL designers are creating increasingly complex designs, and are under relentless pressure to provide assurance that the designs are complete and correct, before handing off the designs for RTL verification and implementation. This assurance needs to be provided at the block/IP level as those become mature enough for handoff, and again once the design is integrated to subsystem or chip level. Recently, the multitude of…
- 12 Nov 2020
Breakfast Bytes: Arm Goes for It

Paul McLellan

At the recent Linley Processor Conference, Arm presented two processors. This was regarded as so confidential that the original pre-conference version of the presentations didn't contain the Arm one, even though that pdf was only put online about an ...
- 11 Nov 2020
Life at Cadence: Think Beyond the Chip

Tom Beckley

Cadence is certainly well-known for our design tools for integrated circuit (IC) design. I run the custom and analog IC part of our business, built around our Virtuoso platform. But that’s not the focus of this post. Instead, I'd like to encou...
- 11 Nov 2020
Verification: Have You Ever Wanted to Learn Specman/e and Did Not Know How?

teamspecman

As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First, when you look for your next exciting verification position, the more HVL you know, the more options you have. In addition, you reflect yourself as a knowledgeable person for potential employers. Secondly, familiarity with several HVL, makes you a better verification…
- 11 Nov 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: チップにとらわれない – ICとICパッケージ設計および検証ツール間におけるクラス最高の相互運用性の優位点

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 10 Nov 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: RF PCB Design Flow Using Allegro Editors

Shreyansh

Allegro® RF PCB solution provides you with a unified design solution for complex mixed-signal projects. From schematic to layout and manufacturing, a total front-to-back design flow helps you streamline your entire RF design process. You lay RF ...
- 10 Nov 2020
Digital Design: Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges

timjedwards

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.
- 10 Nov 2020
System, PCB, & Package Design : IC Packagers: Key Functions for Good SKILL Programming in Allegro Package Designer

Tyler

Many of you out there are SKILL coders (or have these people on your team). SKILL is the extension programming language for all the backend layout products in the Allegro family, including Allegro Package Designer. If you’ve read up on the blog...
- 10 Nov 2020
Analog/Custom Design: Virtuosity: The Debut of the Virtuoso EMIR Analysis Flow for DSPF

Pallabi R

Do you want accurate extraction data for your design, regardless of foundry process and node? Do you want to complete your EMIR setup entirely within the Virtuoso framework? Then explore the new Virtuoso EMIR DSPF flow…
- 10 Nov 2020
Breakfast Bytes: SRC/SIA Decadal Plan for Semiconductors

Paul McLellan

The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) recently put out the Interim Report for the Decadal Plan for Semiconductors. The full report is planned for later in the year. To set some context, here is ...
- 10 Nov 2020
System, PCB, & Package Design : 2019 HF4 Release for Clarity, Celsius, and Sigrity Tools Now Available

SigrityReleaseTeam

The 2019 HF4 production release for Clarity, Celsius, and Sigrity tools is now available for download at Cadence Downloads.
- 9 Nov 2020
Life at Cadence: Computational Software: A New Paradigm for EDA Tools

Corporate

EDA tools have been evolving since the mid-1980s. The development can be broken down into three major phases, and it’s important to understand these three phases to realize where EDA tools are now, where the tools are much more tightly integra...
- 8 Nov 2020
カスタムIC／ミックスシグナル: Virtuosity: Virtuoso ADE Assembler と Explorer を使用したポストレイアウト容量の調査

Custom IC Japan

ポストレイアウトは最近注目の話題になっています。私と他の何人かのエンジニアは過去1年ほどの間これにより非常に忙しくなりました。私たちがVirtuoso® ADE AssemblerとVirtuoso® ADE Explorerに追加した新しくエキサイティングなポストレイアウト機能の一つがSpectre® Classic Simulatorのnetcapレポートを表示する機能です。この機能はIC6.1.8/ICADVM18.1ISR13から利用可能です。 Virtuoso ...
- 5 Nov 2020
Digital Design: Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 2

AbhaRawat

This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.
- 5 Nov 2020
Academic Network: System Design and Verification Training Deep Dive: Part 3

Kira Jones

As we continue the System Design and Verification Online Training deep dive, we’ll be covering C++ and SystemC languages. These courses should be taken after the recommended courses in Part 1 and Part 2, as the previous parts will provided help...
- 5 Nov 2020
Analog/Custom Design: Start Your Engines: The Blog-o-Meter Check - Lap 2

Jommy

This blog summaries the latest five blogs published in the Start Your Engines series.
- 5 Nov 2020
System, PCB, & Package Design : Implement SI and PI in High-Speed Memory Interfaces

Sigrity

Signal integrity (SI) engineers tasked with successfully implementing memory interfaces, such as DDR4 and DDR5, face major challenges in meeting the requirements in a timely fashion. The traditional design workflow typically assumes an ideal power d...
- 5 Nov 2020
Breakfast Bytes: TSMC, Microsoft, Cadence: Signoff in the Cloud

Paul McLellan

As you can guess from the title of this post, TSMC, Cadence, and Microsoft have been working together on signoff in the cloud. Since signoff comes later in the design cycle and is CPU intensive, it is an ideal part of the flow to make use of the clou...
- 5 Nov 2020
Analog/Custom Design: Virtuosity: Conserve Power— Setting up Virtuoso Power Manager

deeptig

This time I am back with a blog that briefly explains how to set up Virtuoso Power Manager before proceeding with low power verification. To run in-design checks, extract the power intent from a design, or run Conformal Low Power checks, you must first provide inputs that are required by the tool for correct identification of design topology and define the set of rules that apply to those design structures. For example…
- 4 Nov 2020
Breakfast Bytes: A Brief History of Cadence IP

Paul McLellan

I actually ran one of the earliest IP businesses, just not at Cadence. When we spun Compass Design Automation out of VLSI Technology, we had the library designers and the library product lines. So that was standard cells, memories, and gate arrays. V...
- 4 Nov 2020
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Unified Libraries — クロスプラットフォームフローへの道を拓く

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 3 Nov 2020

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