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Analog/Custom Design: Virtuosity: Design, Plan, and Analysis - The 3 Sides Of A Coin, Episode 1

colint

Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.
- 3 Nov 2020
System, PCB, & Package Design : BoardSurfers: Allegro In-Design Reflection Analysis: Signal Integrity Simulations on the PCB Canvas

Shirin Farrahi

Reflections happen on Printed Circuit Boards (PCBs) whenever signals encounter an impedance discontinuity, so maintaining constant impedance along all interconnects is always desirable. But it’s not always possible to achieve this. In order to ...
- 3 Nov 2020
System, PCB, & Package Design : IC Packagers: Allegro Package Designer and 3D DXF

Tyler

Hello, all. As we push towards the next major update to the 17.4 release, the team here at Cadence is very busy! We hope you’ll be as excited by the new updates, enhancements, and bug fixes as we are. But until then, there is still plenty of ca...
- 3 Nov 2020
Breakfast Bytes: Jumping Jack Flash

Paul McLellan

This is the second post about non-volatile memory technologies. The first post was EPROM: Chips with Windows. Today we move to flash memory. This was originally invented by Toshiba in 1980 as a derivative of the EEPROM technology discussed in the fir...
- 3 Nov 2020
Breakfast Bytes: Agricultural Electronics

Paul McLellan

In my post Jobs: Farmer I wrote about my experience as a teenager working on the farm owned (actually rented from the Duke of Badminton) by the father of one of my school friends. Electronics were nowhere to be found in those days. I recently watched...
- 2 Nov 2020
PCB、IC封装：设计与仿真分析: 如何在IC封装中连通晶片与球栅阵列封装（BGA）？

TeamAllegro

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年，专注于IC封装与中介层基板设计。同时，参与全Allegro平台、Virtuoso、PVS、OrbitIO及 Innovus产品的核心工作。 space BGA元件的主要作用是将其保护的裸晶（die）的信号经由BGA的焊球重新分配到其所安装的主机PCB上。因此，许多IC封装设计团队都不绘制前端原理图。即使有原...
- 30 Oct 2020
Breakfast Bytes: EPROM: Chips with Windows

Paul McLellan

I like to do the (London) Times crossword most days. For more information on how cryptic crosswords even work, see my offtopic post Aren't All Crosswords Cryptic? There's also a blog where each day the crosswords get analyzed and critiqued,...
- 30 Oct 2020
カスタムIC／ミックスシグナル: Start Your Engines: AMS DesignerとSystemVerilogネットリスタ・フロー用HDL Packageを便利に定義するためのGUI

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Bonjou...
- 30 Oct 2020
Analog/Custom Design: Virtuosity: Conserve Power—A Preamble to Virtuoso Power Manager

deeptig

Power consumption has always been an overriding concern in electronic design. Consumption relates not only to the power used in the circuitry but also involves monitoring the circuit to prevent overheating. The battery life of any electronic product can be a deciding factor in its success. Designers are continually devising innovative methods to ensure minimal power consumption without impacting the performance of their…
- 29 Oct 2020
Life at Cadence: Why I Loved Being a Technical Communications Intern at Cadence!

Rupesh Mainali

Through this blog, I share my experiences as an intern Technical Communications Engineer with the Custom IC and PCB Group (CPG). Read on to find out more about my observations, contributions, and learnings in this team, and how we’re working together in the One-Cadence One-Team spirit to successfully run several customer-focused initiatives. The blog also includes interesting trivia about the achievements made by the…
- 29 Oct 2020
Breakfast Bytes: Jasper User Group: The State of Formal in 2020

Paul McLellan

Last week was the CadenceCONNECT: Jasper User Group conference. Of course, it was a digital event. Normally, the number of attendees is limited by the size of the Cadence building 10 auditorium, but this year there was no physical limit and over 600 ...
- 29 Oct 2020
カスタムIC／ミックスシグナル: Virtuoso Video Dairy : Virtuoso Visualization and Analysis XL のDirect Measurementsアシスタント

Custom IC Japan

プロットや波形の単純な測定値を作成するためだけに長い式を使用したり、振幅、立ち上がり、立ち下がり時間を測定するためにマーカーを使用したりしなければならなかったことはありませんか？それも、この測定値が所定の位置に留まらないかもしれないのに？そうであれば、これらのタスクを単純化する方法を見つけるために、これを読んでください。 IC6.1.8 ISR13とICADVM18.1 ISR13リリースから、Virtuoso Visualization and Analysis XLに新しいDirect M...
- 29 Oct 2020
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Installing Cadence OrCAD and Allegro Products Without Administrative Rights

Shikha Jain

Often organizations do not grant administrative privileges to users on their systems. Performing administrative tasks by standard users can be of greater risk than benefit as this could lead to serious virus and malware infections and catastrophic da...
- 28 Oct 2020
Analog/Custom Design: Spectre Tech Tips: The Value of Spectre X in EMIR Analysis

Stefan Wuensche

EMIR analysis is one of the more challenging fields of circuit simulation. It requires the power and/or signal net parasitics to be preserved for the later IR drop and EM current analysis. At the same time the EMIR analysis requires SPICE accuracy for properly checking the EM currents against the current limits defined by the foundry. The Cadence transistor level EMIR analysis tool is Voltus-Fi XL which uses the Spectre…
- 28 Oct 2020
Breakfast Bytes: GDDR6 and HBM2E on Samsung Foundry — the SAFE Choice

Paul McLellan

Today is the Samsung SAFE forum. SAFE stands for Samsung Advanced Foundry Ecosystem. In the past, I've covered what was said, especially any details on the process and packaging roadmaps. But last year, Samsung decided to uninvite the press (havi...
- 28 Oct 2020
Academic Network: System Design and Verification Training Deep Dive: Part 2

Kira Jones

As we continue this blog series, we’re going to keep looking at System Design and Verification Online Training courses. In Part 1, we went over Verilog language and application, Xcelium simulator, and introduced SystemVerilog. We’ll now d...
- 27 Oct 2020
System, PCB, & Package Design : IC Packagers: Controlling Voids around Critical Signals

Tyler

With greater and greater counts of high-speed and differential pair signals in designs, the ability to control the areas around these nets becomes more important. Adjusting and maintaining the distance to these nets on the same layer as the routing i...
- 27 Oct 2020
Analog/Custom Design: Virtuoso Video Diary: Usability Enhancements in Digital Signals

Udit Rajput

Read through this blog to know more about the usability enhancements made to digital signals in Virtuoso Visualization and Analysis XL.
- 27 Oct 2020
Breakfast Bytes: CadenceLIVE Israel 2020 Preview

Paul McLellan

Coming up on November 3 is CadenceLIVE Israel. Google tells me that date is 16 Heshvan 5781 on the Hebrew calendar, which sounds way cooler. In normal times, I'd be getting on a plane for the 14-hour flight from San Francisco direct to...
- 27 Oct 2020
カスタムIC／ミックスシグナル: 日本語版データシートの一覧はこちら！

Custom IC Japan

ケイデンス製品をご利用のみなさま、そして、これからご利用を検討されるみなさま、先日はCadenceLIVE 2020 Japanにご参加いただき、ありがとうございました。今年は例年とは異なり、オンラインでの開催となりましたが、いかがでしたでしょうか。昨年までは、ケイデンスの社員がツールやフローについてオンデマンドで説明させていただくブースがあり、そこには、パンフレットのようなものが陳列されたラックがあったことを覚えていらっしゃいますか？そのラックには、ケイデンス製...
- 26 Oct 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Full 3D Analysis of Traces and Bond Wires in an RF Module

jgrad

When you are running the EM analysis for an RF module with a wirebonded IC, an important task is to capture the full coupling between the package and the bond wires. Read this blog to know about a quick and effortless way to do this in Virtuoso RF Solution.
- 26 Oct 2020
Breakfast Bytes: Linley Fall Processor Conference 2020

Paul McLellan

Last week was the Linley Group's Fall Processor Conference. The conference opened, as usual, with Linley Gwenap's overview of the processor market (both silicon and IP). His opening keynote was titled Application-Specific Processors Extend Moore's La...
- 26 Oct 2020
Breakfast Bytes: Sunday Brunch Video for 25th October 2020

Paul McLellan

https://youtu.be/_xItRYHmGPw Made on my balcony (camera Carey Guo) Monday: The Start of the Arm Era Tuesday: The Gen Arm 2Z Ambassadors Wednesday: CadenceLIVE India: Best Paper Awards Thursday: Taking Arm Neoverse into 3D with Digital Full Flow Frida...
- 25 Oct 2020
Breakfast Bytes: Elias Fallon ISOCC Keynote on EDA and Machine Learning

Paul McLellan

At 11:10am Korean time this morning, Cadence's Elias Fallon delivered one of the keynotes at ISOCC (International System On Chip Conference). It was titled EDA and Machine Learning: The Next Leap in Semiconductor Design and Productivity. He ...
- 23 Oct 2020
Analog/Custom Design: Start Your Engines: Two Critical Components of Low-Power Mixed-Signal Simulation in AMS Designer

Qingyu Lin

The low-power format, CPF/UPF/IEEE1801, has been very popular in the digital simulation world for over ten years. Nowadays, it is also commonly used in the mixed-signal simulations.
- 22 Oct 2020

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