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Latest Blog Posts

  • カスタムIC/ミックスシグナル: Start Your Engines: UNLでアナログ・ブロックにSpectreネットリストを生成する理由と方法

    Custom IC Japan
    Custom IC Japan
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 AMS Designe...
    • 29 Jun 2020
  • Breakfast Bytes: Yesterday Was Tau Day

    Paul McLellan
    Paul McLellan
    You probably know that 3/14 is Pi Day, since pi (π) starts 3.14 and so matches the date, at least the way it is written in the US but not in the rest of the world. Well, yesterday was Tau Day, 6/28. Tau (τ) is 2π and so is 6.28. Some mathem...
    • 29 Jun 2020
  • Verification: Improving Tests Efficiency Using Coverage Callback (part 2)

    teamspecman
    teamspecman

    In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using-coverage-callback - we shared some ideas about how to employ the new Coverage Callback API for increasing the tests efficiency. This blog shows two more ideas for improving tests, using runtime coverage information.

    Stop the Run After the Goal Is Reached

    The basic concept of Coverage Driven Verification is running many random tests, and…

    • 28 Jun 2020
  • Breakfast Bytes: Sunday Brunch Video for 28th June 2020

    Paul McLellan
    Paul McLellan
    https://youtu.be/va13w0mgAco Made "under the sea" (camera Carey Guo) Monday: Make a DATE for the Alps Next Ski Season Tuesday: vManager: One Manager to Rule Them All Wednesday: Computational Digital Software Thursday: Under the Hood of Genu...
    • 28 Jun 2020
  • Digital Design: Curious About the Newly Released Innovus Implementation System v20.1?

    VNelson
    VNelson

    We recently released the Innovus v20.1 software and you might be interested in learning about what's new or changed in the software.

    Here are some suggestions to get you up to speed:

    1. The best place to find all the details of the changes relative to v19.1, is to refer to the What's New document on the Cadence support site.
    2. If you want a quick intro to the 20.1 graphical user interface, view this demo that I created…
    • 26 Jun 2020
  • System, PCB, & Package Design : BoardSurfers: Allegro In-Design Return Path Analysis: Find and Visualize Return Path Issues

    Shirin Farrahi
    Shirin Farrahi
    Return path issues are common and difficult to diagnose in complex printed circuit board designs. In the worst case, a signal could have no DC return path, and your circuit will be open at the lowest frequencies. In other cases, a poor return path ca...
    • 26 Jun 2020
  • Life at Cadence: My Life at Cadence Video Series: Komal Gujarathi

    Mary Kasik
    Mary Kasik
    Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This third video features Komal Gujarathi, software engineer. The first time I wrote a small program, I was so exci...
    • 26 Jun 2020
  • Breakfast Bytes: Cornami and Trusted Data

    Paul McLellan
    Paul McLellan
    Recently, I wrote about Fully Homomorphic Encryption (FHE from now on) which I think is going to be something big that you will hear lots about in the future. Here's the reason I think it is going to be big. The people who care the most about securit...
    • 26 Jun 2020
  • Academic Network: Digital Design and Signoff Training Deep Dive: Part 3 – Silicon and Signoff Verification

    Kira Jones
    Kira Jones
    We’re excited to share the last blog for the Digital Design and Signoff Training Deep Dive. We’ve shared the courses you need to take for Synthesis and Test, and Implementation, now we’re going to share the courses for Silicon and S...
    • 25 Jun 2020
  • カスタムIC/ミックスシグナル: Start Your Engines: AMSD Flex – 最新のSpectreの機能にすぐにアクセスできます!

    Custom IC Japan
    Custom IC Japan
    Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Bonjou...
    • 25 Jun 2020
  • Breakfast Bytes: Under the Hood of Genus

    Paul McLellan
    Paul McLellan
    From time to time people ask how EDA tools work under the hood. I think the question is more along the lines of "what is all that stuff in the front of my car?" more than "how does ignition advance work?" So here's what's ...
    • 25 Jun 2020
  • 定制IC芯片设计 : Virtuosity:您的版图设计是否结构正确 ?

    KomalJohar
    KomalJohar
    您的设计是否结构正确?阅读此博客,以了解在设计过程中,如何使用宽度间距模式(WSPs),实现结构正确的设计。 WSPs 的追踪线,为快速创建连接线提供指导。定义WSPs以捕获宽度和间距规则,并且确保这些连接线满足捕获到的设计规则。
    • 24 Jun 2020
  • System, PCB, & Package Design : IC Packagers: How to Fix Padstacks that Aren’t Showing All Their Layers

    Tyler
    Tyler
    We talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up. ...
    • 24 Jun 2020
  • Breakfast Bytes: Computational Digital Software

    Paul McLellan
    Paul McLellan
    Cadence has been using the term "computational software" to unify many of the algorithms that underlie EDA tools. I think that the area where this is clearest is the digital full flow, which starts at synthesis, though physical design, and ...
    • 24 Jun 2020
  • Breakfast Bytes: vManager: One Manager to Rule Them All

    Paul McLellan
    Paul McLellan
    Here's a high-level view of verification: If everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage “Begin with the end in mind.” A good plan contains...
    • 23 Jun 2020
  • Analog/Custom Design: Virtuoso Meets Maxwell: Full CellView EM Extraction

    jgrad
    jgrad
    This blog introduces the full cellview extraction feature of the Virtuoso RF Solution that allows you to extract a 3D S-parameter model for a complete layout cellview. Read more...
    • 22 Jun 2020
  • 定制IC芯片设计 : Virtuoso Meets Maxwell: 了解您的举动–我们正在进行芯片、封装和电路板协同编辑

    Steve PDK Lee
    Steve PDK Lee
    该博客介绍了Cadence Virtuoso RF 解决方案中的Edit-in- Concert 技术,它可以帮助设计师们查看和编辑die packages 及其相应的die 布局。
    • 22 Jun 2020
  • Breakfast Bytes: Make a DATE for the Alps Next Ski Season

    Paul McLellan
    Paul McLellan
    It's the Summer Solstice. To be precise, that was on Saturday, the longest day of the year, but Breakfast Bytes doesn't appear at weekends. Surprisingly, the earliest sunrise of the year was on June 13, a week ago. And the latest su...
    • 22 Jun 2020
  • Breakfast Bytes: Sunday Brunch Video for 21st June 2020

    Paul McLellan
    Paul McLellan
    www.youtube.com/watch Made in "cherry blossoms" (camera Carey Guo) Monday: IEEE 1838: Taking Test into the Third Dimension Tuesday: Uncanny Valley: Being Human in the Age of AI Wednesday: Fully Homomorphic Encryption Thursday: On Writi...
    • 21 Jun 2020
  • Academic Network: Digital Design and Signoff Training Deep Dive: Part 2 – Implementation

    Kira Jones
    Kira Jones
    Welcome back to our series, and if you’re new here, thanks for joining us today! We’re going to be looking at another part of Digital Design and Signoff solutions: Implementation. We’ll be building off the recommended courses from o...
    • 18 Jun 2020
  • Analog/Custom Design: Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC Verification

    Lalit Mohan
    Lalit Mohan
    Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel.
    • 18 Jun 2020
  • Breakfast Bytes: On Writing

    Paul McLellan
    Paul McLellan
    Tomorrow is Juneteenth, which commemorates the ending of slavery in the United States. It is a Cadence holiday. Breakfast Bytes will not appear. Today's off-topic post is about how I became a writer. The short answer is "by accident" si...
    • 18 Jun 2020
  • 定制IC芯片设计 : Virtuosity: Automated Device Placement and Routing Flow 中的器件阵列

    Sravasti
    Sravasti
    在此博客中,我将讨论该ADA功能如何成为新APR解决方案不可或缺的一部分。
    • 17 Jun 2020
  • Breakfast Bytes: Fully Homomorphic Encryption

    Paul McLellan
    Paul McLellan
    Do you know what Fully Homomorphic Encryption (FHE) is? When I first heard about it a few years ago, I thought it was something of minor academic interest, like those schemes for giving keys to a group where any 3 of them can decrypt the message but ...
    • 17 Jun 2020
  • System, PCB, & Package Design : IC Packagers: Navigating Your Visible Design

    Tyler
    Tyler
    Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...
    • 16 Jun 2020
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