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System, PCB, & Package Design : IC Packagers: Time-Saving Alternatives to Show Element

Tyler

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...
- 14 Apr 2020
Breakfast Bytes: The Furthest Man Has Been from Earth

Paul McLellan

What is the furthest that man has been from Earth? And who? If I tell you that today is the 50th anniversary of that event, then you will immediately realize that it must be the three astronauts who were on Apollo 13: Jim Lovell, Jack Swigert, and F...
- 14 Apr 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Keeping Things Simple in the Virtuoso RF Solution

kfullerton

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic simulation is an activity where following that advice has enormous payoffs. In this blog I’ll talk about some of my experiences with how Virtuoso RF Solution’s shape simplification feature has helped my customers get significant performance improvements with minimal impacts on accuracy.
- 13 Apr 2020
Breakfast Bytes: John Park Webinar: Is It the Age of the Chiplet?

Paul McLellan

I first started paying attention to 3D packaging many years ago. Every year there was a conference at the Hyatt in Burlingame on the topic. Everyone was convinced that 3D packaging was coming really soon. Here is a Semiwiki post from 2014 that ...
- 13 Apr 2020
定制IC芯片设计 : Virtuosity：回顾2019年Virtuoso ADE Product Suite 及 Virtuoso Visualization and Analysis

shubhangi upadhyay

对于 Virtuoso®ADE Product Suite 和 Virtuoso® Visualization and Analysis 而言，2019 年是非常重要的一年。我们不仅添加了诸如多测试编辑器之类的新功能，而且还重新设计了一些现有表格，以为您提供最佳体验。可靠性设置，激励设置和多工艺仿真就是其中的几个例子。除此之外，我们还新添加了一些版图后仿真相关的增强功能! 今年的另一项重大更新是 Virtuoso®ADE Verifier 与 Cadenc...
- 13 Apr 2020
Breakfast Bytes: Sunday Brunch Video for 12th April 2020

Paul McLellan

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: From Castles and Moats to Zero-Trust Networking Tuesday: The Dynamic Duo Wednesday: Online Support? There's an App for That! Thursday: Designing Chips for Hyperscale Da...
- 12 Apr 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 基础二：DFx规则设定

SDA China

当布线过程中或者布线结束时，发现器件布局不合理，我们将进行繁琐的调整工作。对于复杂PCB，这个调整可能会占用我们整个上午的时间，甚至更久。如果设计者在布局开始时，设定了DFx的相关规则，那么这种问题出现的概率将大幅下降，有效提升设计质量和效率。 “极致PCB设计全流程”第二期基础篇“DFx规则设定”为您详细指导。关注微信公众号“Cadence楷登PCB及封装资源中心”，在微信后台回复关键词“PCB全流程&rd...
- 10 Apr 2020
Digital Design: Joules – Power Exploration Capabilities

Neha Joshi
Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

Is there any scope to improve power consumption of my design?

What is the best-case power?

Pin-point hot spots in my design?

How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based…
- 10 Apr 2020
Digital Design: Exploring Genus-Joules Integration is just a click away!!

Neha Joshi
Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!!

But:

How to do it?

Is there any specific switch required?

What is the flow/script when Joules is used from…
- 10 Apr 2020
Breakfast Bytes: Designing Chips for Hyperscale Data Centers: Tools

Paul McLellan

Yesterday's post, Designing Chips for Hyperscale Data Centers: IP, covered the high-performance IP that is most useful in designing hyperscale cloud data centers. Today, it is the turn of the tools required to design SoCs, boards, and whole systems ...
- 10 Apr 2020
Digital Design: Genus Synthesis Solution – Introduction to Stylus Common UI

Neha Joshi

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences.

A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow…
- 9 Apr 2020
Breakfast Bytes: Designing Chips for Hyperscale Data Centers: IP

Paul McLellan

Last week I wrote two posts about the progression from the first commercial computers to today's hyperscale cloud data centers. Those posts were: Getting to Hyperscale Data Centers: Mainframes to Minicomputers Getting to Hyperscale Data Centers...
- 9 Apr 2020
Digital Design: Quantus' Substrate Noise Analysis Functionality: RF Spurs Impacting Your Performance? Not Anymore!

Hitendra

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence when I visited an acoustic anechoic chamber. I could hear my own heartbeat, vibration of my cells, and the fluids running through my veins. The absence of sound was ...
- 8 Apr 2020
Breakfast Bytes: Online Support? There's an App for That!

Paul McLellan

You are probably working from home. So is pretty much everyone at Cadence, too. This might make getting support a little trickier than normal. No application engineer is going to be dropping by your office on a regular basis...not that you will be t...
- 8 Apr 2020
Learning and Support: Learn SVA If You Know PSL and Learn PSL If You Know SVA

XTeam

Training Bytes, Cadence’s self-paced learning videos, are the solution for you to get immediate answers to your specific questions. No waiting, no cost, no travel! With Training Bytes, you can focus on one topic and get up to speed with just a ...
- 7 Apr 2020
Academic Network: Remotely Using Cadence Tools and Licenses (part 2)

Anton Klotz

After we have shown how to get remote access to Cadence licenses and tools, the next step would be to take advantage of educational material provided by Cadence. These resources are intended to increase your knowledge about Cadence tools and design f...
- 7 Apr 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Loading SKILL Programs Automatically

Shreyansh

Imagine you are on a vacation with your family, and suddenly, your phone starts buzzing. You pick it up and what are you looking at is a bunch of pending, unanswered e-mails. You start recollecting the checklist you had made before taking off only to realize that you haven’t put on the automatic replies!
- 7 Apr 2020
System, PCB, & Package Design : IC Packagers: A New Option in Bond Finger Solder Mask Openings

Tyler

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...
- 7 Apr 2020
Breakfast Bytes: The Dynamic Duo

Paul McLellan

In the DC Comics world, the "Dynamic Duo" are Batman and Robin. In the Cadence product world, they are the Palladium and Protium platforms. Or Palladium Z1 and Protium X1 to give their last names, too. The Palladium Z1 provides emulation, ...
- 7 Apr 2020
Digital Design: Innovus Implementation System: What Is Stylus UI?

VNelson
Hi Everyone,

Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI.

The webinar answers the following questions:

Why did Cadence develop Stylus UI and what is Stylus Common UI?

How does someone invoke and use the Stylus Common UI?

What are some of the important and useful features of the Stylus Common UI?

What are the key…
- 6 Apr 2020
Analog/Custom Design: Virtuoso Meets Maxwell: What About My Die That Has No Bumps, Only Pad Shapes? How Do I Export That?

Kabir

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.
- 6 Apr 2020
Breakfast Bytes: From Castles and Moats to Zero-Trust Networking

Paul McLellan

The way that we handle enterprise security has changed dramatically. In the days of desktop computers and no internet, we divided the world into two: the castle, and outside, with a moat dividing the two. The moat and its associated drawbridge was t...
- 6 Apr 2020
定制IC芯片设计 : Virtuoso视频日记：“Training bytes”助推知识传播—第1部分

Dishika Majumdar

本文将以简短的方式介绍 Cadence Education Services网站，让您了解其已上线的一些在线培训课程以及Virtuoso产品特定功能相关的文章。
- 6 Apr 2020
Breakfast Bytes: Sunday Brunch Video for 5th April 2020

Paul McLellan

www.youtube.com/watch Made in my living room (camera Carey Guo) Monday: RSA: Emerging Threats, Ransomware, and IoT Tuesday: Linley Spring Processor Conference—In Your Own Living Room Wednesday: The Integrand Story Thursday: Getting to Hyperscal...
- 5 Apr 2020
Breakfast Bytes: Getting to Hyperscale Data Centers: PCs to Clouds

Paul McLellan

This post is a continuation of yesterday's post, Getting to Hyperscale Data Centers: Mainframes to Minicomputers. It continues the story from minicomputers to PCs, and then to today's environment of hyperscale data centers for "big iron...
- 3 Apr 2020

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