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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Digital Design

Library Characterization Tidbits: Liberate MX for Memory Characterization Video …

As we embark upon our blogging journey again in 2020, in this Library Characterization…

• 3 min read
Liberate MX validation flow , memory characterization , liberate_mx custom flow , standard custom flow , full custom flow , liberate_mx standard custom flow , compiler characterization , liberate_mx full custom flow , liberate_mx , Liberate MX , Characterization Portfolio

Breakfast Bytes

Benedict Evans 2020: Standing on the Shoulders of Giants

For the last five or six years, Benedict Evans worked at Andreesen-Horowitz (a16z…

• 5 min read
benedict evans , Internet , mobile

Breakfast Bytes

Sunday Brunch Video for 9th February 2020

https://youtu.be/CVbxaO8cVoM Made in Steve's office (camera Steve Brown) Monday…

• less than a min read
sunday brunch

Academic Network

Certified TowerJazz-Cadence Analog Lab at KPI in Ukraine

Around one year ago TowerJazz VP, Ori Galzur, contacted us and suggested to start…

• 3 min read
Cadence Academic Network , Certified Lab , KPI , Ukraine , TowerJazz

Analog/Custom Design

Virtuosity: Blogging Journey of Virtuoso Place and Route in 2019

To support various new features and enhancements in Virtuoso Placement and Routing…

• 6 min read
tree routing , Modgen On Canvas , structured routing , ICADVM18.1 , Virtuoso Space-based Router , EXL , mesh routing , MODGEN , Automated Device-Level Placement and Routing , Virtuoso Placer , Layout EXL , trunk-to-trunk mesh , Auto P&R , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Finish Trunk , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

How Is the C Compiler Written in C?

Often compilers for computer programming languages are written in their own language…

• 7 min read
llvm , compiler , C++

Computational Fluid Dynamics

Boom Supersonic: Relaunching Commercial Supersonic Aircraft Travel

Authors: Michael Rybalko, Aeropropulsion Engineer, Boom Supersonic & Jean-Charles…

• 5 min read
CFD , NUMECA

Breakfast Bytes

Exadata: An Epic Journey at Oracle with Persistent Memory

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent…

• 5 min read
persistent memory summit , exadata , Oracle , optane , persistent memory

Verification

A Specman/e Syntax for Sublime Text 3

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab…

• 1 min read
Specman , Specman/e , Specman e , Sublime Text , specman elite

Breakfast Bytes

The Signal Integrity Story

Yesterday, I started to talk about how new technologies find their way over time…

• 5 min read
celsius , CadMOS , Signal Integrity , Sigrity , clarity

System, PCB, & Package Design 

IC Packagers: A Boundless Bounty of Bounding Shapes

How’s that for a tongue twister? Go ahead, try and say it three times fast! What…

• 4 min read
Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: High-Speed Design Signal Integrity Challenges and Solutions

Usually, people start a blog by stating something dramatic and we used to bring drama…

• 3 min read
Sigrity , Allegro PCB Editor

Breakfast Bytes

How Technologies Get into EDA

When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different…

• 6 min read
sales , startups , ambit , Signal Integrity , salesforce

Breakfast Bytes

Persistent Memory at Twitter

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent…

• 3 min read
persistent memory summit , Oracle , optane , Twitter , persistent memory

Verification

USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic…

• 1 min read
Verification IP , DP , DisplayPort , USB , usb4 , PCIe , tunneling

Breakfast Bytes

Persistent Memory: We Have Cleared the Tower

Last week it was the Persistent Memory Summit 2020, which has been running annually…

• 7 min read
persistent memory summit , persistent memory , 3dxpoint

Breakfast Bytes

Quarry Bank Mill: A Technology Museum from the Industrial Revolution

A couple of years ago (and from time to time since) I wrote a series of blog posts…

• 5 min read
industrial revolution , museum

Breakfast Bytes

Sigrity Aurora: In-Design Analysis

Cadence's new Sigrity Aurora puts all the power of the Sigrity engines under the…

• 3 min read
Sigrity Aurora , Signal Integrity , Sigrity

Life at Cadence

Intelligent System Design

Electronics technology is proliferating to new, creative applications and appearing…

• 9 min read
intelligent system design
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